A compact quantum random number generator (QRNG) based on an array of Single Photon Avalanche Diodes (SPADs) is presented here. The main feature of the proposed chip is the capability to generate random numbers without the use of any external source of light. In this view, SPADs are configured to be used in two ways: 1) as a controlled light emitter and 2) as a detector. An embedded logic is able to distinguish dark events against detected emitted photon in such a way to make the system sensitive only to the presence of light. The extracted random bits show a uniform distribution and the QRNG, thanks to an integrated conditioning block maximizing the output entropy, eventually passes all AIS31 tests. The average raw bit rate in the default device configuration (one enabled column) is measured equal to 800 kbps.

The present paper describes a time-based technique for resistive detector. Thanks to the comparison with a reference resistance, the circuit easily compensate the baseline contribution, thus extending the dynamic range of the measurement. The implemented circuit is based on a resistance to time converter followed by a time comparator for signal comparison. Differently from existing time-based technique, the proposed approach allows increasing the sensitivity of the detection by increasing the time of the measurement. The circuit exhibits a measured resolution in the order of 20ppm with a nominal value of resistance of about 3MΩ while the maximum dynamic range is of about 40dB.

A CMOS front-end for fast amplification triggering and integration of signals produced by a Silicon Photomultiplier (SiPM) coupled with a LYSO scintillator is presented. This solution is ideal for Positron Emission Tomography (PET), where good timing resolution is required. This design is realized in 0.15μm CMOS process. The front-end features a low input impedance of 4.5Ω and high bandwidth of 100MHz with a total power consumption of 10.6mW.

A 64x64 pixel vision sensor performs adaptive background subtraction and event detection at very low power consumption. The chip is based on a VLSI-oriented vision algorithm, implemented at pixel-level, mimicking the basic process of pre-attentive visual perception. Anomalous pixel behaviors are detected and coded into a 2-bit/pixel. Each pixel integrates two programmable Switched-Capacitors Low-Pass Filters and two clocked comparators, which are fundamental blocks for the execution of the vision algorithm. The 45T square pixel has a pitch of 26μm and a fill factor of 12%. The vision sensor consumes 33μW at 13 fps and 3.3V. This turns into a computing performance of 42 GOPS/W and 4 GOPS/mm2, which are values aligned with the most advanced computational vision sensors.

The presented demonstrator implements a person counting system using a single overhead sensor and counting the number of people going in and out of an observed area. It is based on a low-power vision sensor, which extracts the contrast of the image in a binary form, implements motion by differencing two successive frames and dispatches the asserted pixels through an address-driven data representation. A lightweight counting people algorithm has been developed, which is based on virtual loop. The demonstrator consists of the vision sensor interfaced with the FPGA and linked to a PC with a graphical interface.

The presented demonstrator is capable of detecting a user-defined amount of motion in a scene with a limited energy-budget. This makes it suitable to be used as an energy- autonomous vision sensor for a wireless sensor network. It consists of a low-power contrast-based CMOS vision sensor interfaced with an FPGA and linked to a PC through the USB. The low-power vision sensor directly extracts the visual contrast of images in binary form and estimates the motion in the scene through a temporal matching, without dispatching any pixel outside the chip. The amount of moving pixels between two successive frames is computed by the sensor and compared outside the chip, with respect the a user-programmed value, by means of the FPGA, This low-power operating mode takes about 60 muW at a frame rate of 50 fps and does not occupy any data bandwidth.

A novel algorithm for high intra-scene dynamic-range images representation is here proposed, which is based on Address Event Representation (AER) visual data. The values of the spiking pixels coming from the sensor are dynamically mapped into an 8-bit output, providing a real-time equalization of the scene. The algorithm has been tested using an AER emulator, based on a time-to-first spike imager. The simple implementation of the proposed technique makes it particularly suitable for AER sensors, turning into a real time processing and large programmability on the output tone mapping.

A prototype of a 34 x 34 pixel image sensor, implementing real-time analog image processing, is presented. Edge detection, motion detection, image amplification, and dynamic-range boosting are executed at pixel level by means of a highly interconnected pixel architecture based on the absolute value of the difference among neighbor pixels. The analog operations are performed over a kernel of 3 x 3 pixels. The square pixel, consisting of 30 transistors, has a pitch of 35 microm with a fill-factor of 20%. The chip was fabricated in a 0.35 microm CMOS technology, and its power consumption is 6 mW with 3.3 V power supply. The device was fully characterized and achieves a dynamic range of 50 dB with a light power density of 150 nW/mm2 and a frame rate of 30 frame/s. The measured fixed pattern noise corresponds to 1.1% of the saturation level. The sensor's dynamic range can be extended up to 96 dB using the double-sampling technique.