In this paper we propose a new algorithm for finding shortest paths in a tile connection graph. This algorithm uses an exact piecewise linear cost model to guide our search of the compact tile graph. Unlike previous tile search algorithms, this algorithm always rinds a shortest path. Unlike the grid graph algorithms (which do find shortest paths), this algorithm searches the tile graph which is much smaller than the grid graph. The efficiency of our new approach is confirmed by our experiments comparing our new algorithm with the grid graph algorithms.

In this paper, based on tile connection graph, we propose an efficient minimum cost path search algorithm through tile obstacles. This search algorithm is faster than previous graph based algorithm and unlike previous tile based algorithms, this algorithm finds the minimum cost path.

Asymptotic waveform evaluation (AWE) is a waveform estimation technique which involves the computation of moments from a linear circuit followed by the generation of waveform estimates based on those moments. During moment computation a special case arises if there are capacitor cutsets or inductor loops. Methods proposed for handling these cases involve identifying the cutsets and loops and replacing one of the capacitors (inductors) with a dependent source. This note describes a different formulation of the problem. The elimination of redundant equations in order to compute moments can be viewed as the dual of the problem of reducing circuit equations to normal form. This formulation has a couple of interesting theoretical properties: (1) it formally handles all circuit topologies, including circuits with dependent sources for which the redundancies may be undetectable from an inspection of the circuit topology; and (2) it predicts that even networks without independent sources may have "hidden" particular solutions consisting of polynomials in t.>

Rsim is a switch-level simulator that can simulate large digital MOS integrated circuits up to three orders of magnitude faster than SPICE. Unfortunately, Rsim's simplified circuit models and timing analysis prevent it from simulating "difficult" CMOS circuits and circuits containing bipolar transistors. We address this shortcoming by adapting Rsim to use more general piecewise linear models. We show that these modifications can be made in a way that preserves Rsim's efficiency for the simplest cases. The result is a simulator that can approach the efficiency of dedicated switch-level simulators when switch-level models are used. Alternatively, greater accuracy and flexibility can be obtained when more sophisticated models are used.>

Rsim is a switch-level simulator which can simulate large digital MOS integrated circuits with speedups of over three orders of magnitude over SPICE. Unfortunately, Rsim's simple switched-resistor model renders it incapable of simulating certain CMOS and most BiCMOS and ECL digital circuits. We observe that the switched-resistor model is just one particular piecewise linear model and that Rsim's simulation framework can accommodate more elaborate piecewise linear models. The resulting simulator, Mom, combines the efficiency of switch-level simulation with the ability to simulate a wider variety of circuits. We demonstrate Mom's efficiency and flexibility on a variety of circuits.

Bisim is an event-driven, transistor-level, logic simulator that models both the logical and timing characteristics of custom emitter-coupled-logic/current-mode-logic circuits. Node voltages are represented by piecewise-linear waveforms, transistor currents are represented by piecewise-constant waveforms, and transistors are modeled as voltage-controlled current switches. Bisim's realistic circuit models enable it to simulate correctly a wide variety of circuit topologies while retaining much of the speed of higher level simulators.>