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Robert M. Lougheed

dblp:05/3269 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorArtificial intelligence and machine learning · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 52% Hardware accelerators and domain-specific architectures · 31% Processor architecture and microarchitecture · 13%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › layout verification
design rule checking		 0.011982
Cellular image processing techniques for VLSI circuit layout validation and routing · DAC 1982
Electronic design automation
physical design		 0.011982
Cellular image processing techniques for VLSI circuit layout validation and routing · DAC 1982
Electronic design automation › physical design
routing		 0.011982
Cellular image processing techniques for VLSI circuit layout validation and routing · DAC 1982
Hardware accelerators and domain-specific architectures
image processing accelerator		 0.011980
The Cytocomputer: A Practical Pipelined Image Processor · ISCA 1980
Hardware accelerators and domain-specific architectures › image processing accelerator
pipelined image processor		 0.011980
The Cytocomputer: A Practical Pipelined Image Processor · ISCA 1980
Processor architecture and microarchitecture › pipelining
pipelined processor		 0.011980
The Cytocomputer: A Practical Pipelined Image Processor · ISCA 1980
Parallel and multicore computing › array processor
parallel array processor		 0.011980
The Cytocomputer: A Practical Pipelined Image Processor · ISCA 1980

Methods — techniques the papers use, named apart from their topics

pipelined processing · 0.0cellular image processing · 0.0
YearPublicationVenuePosition
1988 3-D imaging systems and high-speed processing for robot control
Robert M. Lougheed, Robert E. Sampson
 Mach. Vis. Appl.1
1985 Multi-Processor Architectures For Machine Vision and Image Analysis
Robert M. Lougheed, David L. McCubbrey
 ICPP1
1982 Cellular image processing techniques for VLSI circuit layout validation and routing
abstract
The architecture of the Cytocomputer?, an existing special-purpose, pipelined cellular image processor, is described. A formalism used to express cellular operations on images is then given. Cellular image processing algorithms are then developed that perform (1) design rule checks (DRC's) on VLSI circuit layouts, and (2) Lee-type wire routing. Two sets of cellular image processing transformations for checking the Mead and Conway design rules and for Lee-routing have been defined and used to program the Cytocomputer. Some experimental results are shown for these cellular implementations.
Trevor N. Mudge, Rob A. Rutenbar, Robert M. Lougheed, Daniel E. Atkins
 DAC3
1980 The Cytocomputer: A Practical Pipelined Image Processor
abstract
This paper presents a new architecture for image processing. It consists of a pipeline of identical programmable serial processing stages, referred to as a cytocomputer. Comparisons are made between cytocomputer and parallel array systems. Cytocomputer systems are shown generally to possess the advantages of lower complexity, high bandwidth and greater architectural flexibility. A first generation system is described and examples of processing are illustrated. Finally, current development efforts are described.
Robert M. Lougheed, David L. McCubbrey
 ISCA1