Even though decimal arithmetic is pervasive in financial and commercial transactions, computers are still implementing almost all arithmetic calculations using binary arithmetic. As chip real estate becomes cheaper it is becoming likely that more computer manufacturers will provide processors with decimal arithmetic engines. Programming languages and databases are expanding the decimal data types available while there has been little change in the base hardware. As a result, each language and application is defining a different arithmetic and few have considered the efficiency of hardware implementations when setting requirements. We propose a decimal format which meets the requirements of existing standards for decimal arithmetic and is efficient for hardware implementation. We propose this specification in the hope that designers will consider providing decimal arithmetic in future microprocessors and that future decimal software specifications will consider hardware efficiencies.

The first high performance floating point unit to support both IBM 360 hexadecimal based floating point architecture and the IEEE 754 Standard binary floating point architecture is described. The S/390 G5 floating point unit supports the new S/390 architecture which includes hexadecimal based short, long, and extended precision formats and IEEE 754 standard single, double, and quad formats. This floating point unit is part of the microprocessor chip on the S/390 G5 mainframe computer introduced in 1998 and generally available at 500 MHz speeds. The S/390 G5 represents the current state of the art in CISC processor design. The paper describes the S/390 architecture enhancements, the internal format of the FPU, and the modifications to the FPU dataflow.

The considerations that shaped the architecture of the IBM System/370 Vector Facility are reviewed. The architectural requirements, decisions, and innovations are summarized, and the rationale for the choices that were made is given. Issues related to vector function, performance, compatibility, migration, and integration with the rest of the System/370 architecture are covered.>

This paper discusses the performance, complexity and system-integration considerations that shaped the System/370 Vector Architecture [1, 9]. The architecture is intended for compatible systems providing a range of price and performance. The paper reviews the reasons for choosing a register-oriented architecture with compound instructions over storage-to-storage operations and vector-instruction chaining. Then it discusses the role of cache in stride-N storage accessing, and describes some new facilities introduced for control-program purposes.