Conventional CMOS scaling and the Moore's law have been the cornerstone of progress in computing hardware technology. However, with dimensional scaling expected to end soon, there is a pressing need to find the next information processing hardware that can continue to support the technology revolution. Will this hardware solution be an enhanced or an augmented version of MOSFET or a switch based on a radically new switching mechanism. Ultimately, do we require a complete deviation from the Boolean paradigm itself? In this invited paper, we will review some of the actively pursued future logic, merged logic-memory and related concepts.

No abstract available.

As transistor gate lengths are scaled towards the 10-nm range, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the transistor drain region, which may increase the drain series and source injection electrical resistances. Such trends are accelerated by the introduction of novel materials and nontraditional transistor geometries, including ultrathin body, FinFET, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomena including ballistic electron transport, which reshapes the heat generation region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. This paper surveys trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems

Thermal simulations are important for advanced electronic systems at multiple length scales. A major challenge involves electrothermal phenomena within nanoscale transistors, which exhibit nearly ballistic transport both for electrons and phonons. The thermal device behavior can influence both the mobility and the leakage currents. We discuss recent advances in modeling coupled electron-phonon transport in future nanoscale transistors. The solution techniques involve solving the Boltzmann transport equation (BTE) for both electrons and phonons. We present a practical method for coupling an electron Monte Carlo simulation with an analytic "split-flux" form of the phonon BTE. We use this approach to model self-heating in a 20 nm quasi-ballistic n+/n/n+ silicon diode, and to investigate the role of hot electron and hot phonon transport.