EDBT 2026 Demo / reviewers in the wild / expert
Ravindra Nair
dblp:05/4211
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1979
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 91% Memory systems · 9% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 2 | 1979 | Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" · IEEE Trans. Computers 1979 Efficient Algorithms for Testing Semiconductor Random-Access Memories · IEEE Trans. Computers 1978 |
Electronic design automation › hardware verification and test
memory testing |
0.0 | 2 | 1979 | Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" · IEEE Trans. Computers 1979 Efficient Algorithms for Testing Semiconductor Random-Access Memories · IEEE Trans. Computers 1978 |
Electronic design automation › hardware verification and test › fault testing
stuck-at fault testing |
0.0 | 1 | 1979 | Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" · IEEE Trans. Computers 1979 |
Electronic design automation › hardware verification and test › fault modeling
functional fault model |
0.0 | 1 | 1978 | Efficient Algorithms for Testing Semiconductor Random-Access Memories · IEEE Trans. Computers 1978 |
Memory systems
random-access memory |
0.0 | 1 | 1979 | Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" · IEEE Trans. Computers 1979 |
Methods — techniques the papers use, named apart from their topics
test sequence generation · 0.0fault detection algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1979 | Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"abstractAn efficient, optimal test sequence for detecting multiple stuck-at faults in random access memories (RAM's) for any decoder implementation is presented. Another algorithm which does not assume any particular wired logic behavior of simultaneously accessed storage locations, is also presented. Ravindra Nair |
IEEE Trans. Computers | 1 |
| 1978 | Efficient Algorithms for Testing Semiconductor Random-Access MemoriesabstractA fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented. An efficient 0(n) algorithm to detect all faults in the fault model is described. The fault model is then extended to incorporate more complex faults. An 0(n · log2 n) algorithm is presented for one such extended fault model. Ravindra Nair, Satish M. Thatte, Jacob A. Abraham |
IEEE Trans. Computers | 1 |