Garbage collection (GC) is ubiquitously used to reclaim useful space during the data update process in NAND flash memories. Conventional GC algorithms keep track of a table storing the number of valid pages in each block and select ones with the smallest number of valid pages to erase. We notice that NAND flash not only stores user data but also keeps updating meta data frequently and one of the most important requirements of GC for meta data updates is latency predictability, which means the latency of GC should not only be low on average and on tail distributions, but also independent of workload, i.e., the sequence of meta data updates. It is also desirable to have all NAND pages/blocks written the same number of times to avoid any latency incurred by wear leveling. In this paper, we propose GC algorithms that do not require any look-up tables, which avoids the latency for reading the table and sorting the number of valid pages, and intrinsically enables all pages to be worn equally. Several GC algorithms are proposed to make trade-offs between over-provisioning and write amplification. We also provide sufficient and necessary conditions that the proposed GC algorithms will not encounter a deadlock, i.e., the algorithms can run continuously on all meta data update sequences without data loss.

In amplify‐and‐forward relay networks, accurate channel estimation of individual links is essential for coherent reception and optimal design. To acquire the channel state information of individual links, a novel in‐band superimposed training is proposed, where relay superimposes its own training sequence directly on top of the information‐bearing received data. As a result, the training sequences from the source and relay nodes are independent of each other, thus making it more flexible and robust in relay‐training design. However, the proposed training scheme induces extra data interference that degrades the estimation performance. The authors first adopted the detected symbols to mitigate the data‐induced interference during channel estimation. However, the estimation performance is degraded by the symbol detection error and relay propagated noise. To resolve this problem, the interference nulling at the relay is proposed, where some special frequency components of the received data are nulled prior to training superimposition. As a result, both the data‐induced interference and relay propagated noise are totally removed during channel estimation. Simulation results are provided to assess the performance of the proposed schemes.

In this letter, we consider the inter-relay interference (IRI) problem for amplify-and-forward (AF) two-path successive relay networks. To reduce processing burden for IRI cancelation at the relay nodes, a novel precoding-based interference cancelation scheme based on row-space mapping is proposed, where a pair of orthogonal precoding matrices is alternately utilized to project the source data onto the null space of the received data that is independent of channel state information (CSI). By designing a combined decoding and re-encoding scheme, both the IRI signal and accumulated noise are perfectly suppressed at the relay nodes. Simulation results show that the proposed scheme is significantly better than the channel estimate based interference cancelation schemes.

Rabin fingerprints are short tags for large objects that can be used in a wide range of applications, such as data deduplication, web querying, packet routing, and caching. We present a pipelined hardware architecture for computing Rabin fingerprints on data being transferred on a high throughput bus. The design conducts real-time fingerprinting with short latencies, and can be tuned for optimized clock rate with "split fresh" technique. A pipelined sampling logic selects fingerprints based on the Minwise theory and adds only a few clock cycles of latency before returning the final results. The design can be replicated to work in parallel for higher throughput data traffic. This architecture is implemented on a Xilinx Virtex-6 FPGA, and is tested on a storage prototyping platform. The implementation shows that the design can achieve clock rates above 300 MHz with an order of magnitude improvement in latency over prior software implementations, while consuming little hardware resource. The scheme is extensible to other types of fingerprints and CRC computations, and is readily applicable to primary storages and caches in hybrid storage systems.

Data deduplication has proven important in backup storage systems as large amount of identical or similar data chunks exist. Recent studies have shown the great potential of data deduplication in primary storage and storage caches. Deduplications in these environments require high speed processing not to drag down production performance. This paper presents a hardware accelerator for similarity based data deduplication. It implements three compute-intensive kernel modules to improve throughput and latency in dedupe systems: sketch computation for data blocks, index searching for reference block, and delta encoding over similar blocks. Adopting pipelined computation and parallel data lookup across multiple hardware modules, our HW design is capable of processing high throughput data traffic by working on multiple data units concurrently, thus enabling wire speed dedupe for data stream where similar blocks present. Using a PC host system connected to the FPGA-based accelerator through a PCIe Gen 2×4 interface, our experiments show that the similarity based data dedupe performs 30% better in data reduction ratio than conventional dedupe techniques that look at identical blocks only. By comparing the hardware implementation with its software counterpart, the experimental results show that our preliminary FPGA implementation with maximum clock speed of 250MHz achieves at least 6 times improvement in latency over the software implementation running on state-of-art servers.

Visible light cameras commonly used for surveillance applications usually have a limited field of view (FoV). To acquire a broader FoV, distributed aperture systems (DASs) combine views from multiple cameras. Although some commercial or proprietary systems already exist, the open literature in this field reports solely the performance and/or hardware architecture of the respective systems, and omits the required details for a reimplementation. In this paper we present a low-cost, personal-computer-based 360° DAS, with a full description of the hardware architecture and the software implementation details. In particular, we describe in detail two problems, the offline estimation of the orientations of the cameras of the proposed DAS and the online synthesis of a virtual view in real time. For the first problem, we propose an area-based bundle adjuster by combining the forward additive Lucas-Kanade algorithm with a bundle adjustment strategy. The color virtual view of up to 2048 × 1024 pixels is synthesized online at 39 frames/s. A large majority of the workload of the online phase is implemented on the graphic processing unit. The techniques and methods proposed in this paper are generic and independent on the arrangement of cameras.

Visible light cameras are commonly used for surveillance applications. However, a single camera can only provide a limited field of view (FOV). To overcome this problem, distributed aperture systems (DAS) are developed to provide a broader FOV by combining the views from multiple cameras. In this paper, we present a personal-computer-based 360 degree vision DAS system, and describe how to offline estimate the orientations of the cameras constituting the DAS system, as well as online synthesize a virtual view in real time. Our system is able to synthesize a color virtual view of up to 2048×1024 pixels at a speed of 39 frames per second (fps). A large majority of the workload of the online synthesis of the virtual view is implemented on the Graphic Processing Unit (GPU).

Dynamic provisioning is a useful technique for handling the virtualized multi-tier applications in cloud environment. Understanding the performance of virtualized multi-tier applications is crucial for efficient cloud infrastructure management. In this paper, we present a novel dynamic provisioning technique for a cluster-based virtualized multi-tier application that employ a flexible hybrid queueing model to determine the number of virtual machines at each tier in a virtualized application. We present a cloud data center based on virtual machine to optimize resources provisioning. Using simulation experiments of three-tier application, we adopt an optimization model to minimize the total number of virtual machines while satisfying the customer average response time constraint and the request arrival rate constraint. Our experiments show that cloud data center resources can be allocated accurately with these techniques, and the extra cost can be effectively reduced.

Breadth-first Search (BFS) is a fundamental graph problem. Due to the irregular nature of memory accesses to graph data structures, parallelization of BFS on cache-based systems leads to poor performance. Many issues, such as memory access latency, cache coherence policy, and inter-process synchronization, affect the throughput performance of BFS on such systems. In our proposed message-passing multi-softcore architecture, parallelization is achieved by exchanging information among autonomous softcores on FPGA. Several optimizations are performed to reduce the traffic on the interconnect and to enable designs with high clock rates. Implementations on a state of the art FPGA achieve clock rates in excess of 100 MHz. The sustained performance of our system ranges from 160 to 795 Million Edges Per Second on a DDR3 DRAM. This result approaches the upperbound set by the DRAM bandwidth, and it rivals the best performance from implementations on various multi-core computing platforms.

FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such large dictionaries can be stored in external DRAM only. The increased memory latency and limited bandwidth pose new challenges to FPGA-based designs, and the lack of spatial and temporal locality in data access also leads to low utilization of memory bandwidth. In this paper, we propose a multi-core architecture on FPGA to address these challenges. We adopt the popular Aho-Corasick (AC-opt) algorithm for our string matching engine. Utilizing the data access feature in this algorithm, we design a specialized BRAM buffer for the cores to exploit a data reuse existing in such applications. Several design optimization techniques are utilized to realize a simple design with high clock rate for the string matching engine. An implementation of a 2-core system with one shared BRAM buffer on a Virtex-5 LX155 achieves up to 3.2 Gbps throughput on a 64 MB state transition table stored in DRAM. Performance of systems with more cores is also evaluated for this architecture, and a throughput of over 5.5 Gbps can be obtained for some application scenarios.

With the emerging technologies like cloud computing and Internet scale data centers, radically simplified deployment approaches are critical for the success of the even more complicated solutions. Although there have been many traditional solution deployment approaches, each of them mainly focuses on particular software type or product. In this paper, we propose the next generation solution deployment paradigm as hybrid solution deployment, which enables fast solution deployment from bare metal mode to production mode based on todaypsilas state-of-the-art provisioning tools. Solution provisioning automation (SPA) framework is our practice of such deployment paradigm. In SPA, we use solution template to capture the solution components and their dependencies, which exposes only the necessary parameters for users to customize. Provisioning Requests are placed through reservations and scheduled globally for execution. The SPA engine receives provisioning requests from scheduler, interprets the solution template, manages provisioning tasks and performs runtime logging. We also present a real world case to demonstrate the effectiveness of our approach.

Reconfigurable computing systems have been built that combine FPGAs and general-purpose processors to achieve high performance. The nodes in these systems can have different compute capacities based on the processors and FPGAs within them. In this paper, we study the algorithm design on heterogeneous reconfigurable systems for two key linear algebra kernels: matrix multiplication and LU decomposition. Our designs exploit the heterogeneous nodes and utilize up to 80% of the compute capacity of the system.

To catch up with today's fast changing business markets, web services has never slowed down its paces for evolution. As a consequence, service consumers have to employ in-time upgrades to guarantee continuous business integrity and avoid unnecessary runtime errors in their IT systems. However, a new web service release can involve hundreds of changes, and thus it is non-trivial for the service consumer to rapidly track and adopt relevant changes. This paper proposes a framework for facilitating the service consumer to keep synchronized with the web service evolution. On the service side, a Service Invocation Monitor is installed to monitor the interaction history of the client, a Service Delta Analyzer exports the service delta into well-formatted document, and a Release Note Customizeris configured to customize the full release note produced using the monitored interaction history and exported service delta. On the client side, the Consumer Code Customizer is used by the consumer developer to highlight the code fragments to be changed and provide facilitation linkages between the code fragments and the customized release note. An example is shown to demonstrate the usefulness of our proposal.

Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end routers, they do not scale well for the next-generation. On the other hand, pipelined SRAM- based algorithmic solutions become attractive. Intuitively multiple pipelines can be utilized in parallel to have a multiplicative effect on the throughput. However, several challenges must be addressed for such solutions to realize high throughput. First, the memory distribution across different stages of each pipeline as well as across different pipelines must be balanced. Second, the traffic on various pipelines should be balanced. In this paper, we propose a parallel SRAM-based multi- pipeline architecture for terabit IP lookup. To balance the memory requirement over the stages, a two-level mapping scheme is presented. By trie partitioning and subtrie-to-pipeline mapping, we ensure that each pipeline contains approximately equal number of trie nodes. Then, within each pipeline, a fine-grained node-to-stage mapping is used to achieve evenly distributed memory across the stages. To balance the traffic on different pipelines, both pipelined prefix caching and dynamic subtrie-to-pipeline remapping are employed. Simulation using real-life data shows that the proposed architecture with 8 pipelines can store a core routing table with over 200 K unique routing prefixes using 3.5 MB of memory. It achieves a throughput of up to 3.2 billion packets per second, i.e. 1 Tbps for minimum size (40 bytes) packets.