RISC-V devices are widely used in diverse IoT applications, where security is critical. Control flow hijacking attacks can circumvent existing security mechanisms to transfer the program control flow to harmful gadget chains arranged by adversaries, which are primarily initiated by tampering with the data frame and return address within the stack. In this work, we present a microarchitecture-level, hardware-assisted, lightweight scheme for encrypting and verifying stack integrity, thereby transparently enforcing runtime control-flow integrity. The encrypted stack hinders attackers’ analysis and increases the difficulty of assembling malicious gadgets. Stack integrity verification enables the system to detect malicious actions that tamper with return addresses and crucial registers at runtime. We implement the system on an Xilinx XC7K325T FPGA with the T-head Xuantie E906 RISC-V core. The experimental results show that, with a 16KB D-Cache across the ten selected benchmark sets, this work incurs an average performance overhead of 4.89%. At the same time, the CoreMark score decreases by merely 0.10%. The area introduced by the proposed hardware is 10.01% of the total SoC under SAED 32nm Technology.

Mobile Edge Computing (MEC) has been successful in proving solid support for delay-sensitive and computation-intensive applications, while invoking channel forecast enlightens a new dimension to further improve the performance. However, separately considering channel forecast and resource management fails in fully exploiting the merit of channel forecast. In this paper, we proceed in two steps. 1) By incorporating channel forecast, we extend the conventional Lyapunov optimization into multi-step-ahead Lyapunov optimization to minimize the queueing delay for non-causal scenario. 2) Based on the obtained insights, we tailor the conventional Long Short Term Memory (LSTM) into Differentiated Randomly Connected LSTM (DR-CLSTM) to obtain a desired trade-off between model complexity and forecast accuracy for the sake of delay minimization. Our simulation results highlight the performance gain of the proposed framework in terms of the system delay.

Millimeter-wave (mmWave) vehicular communication brings new technical challenges on wireless resource management due to the sensitivity to blockages and the directionality property, as conventional beam alignment techniques suffer from large communication overhead. To enable fast base station (BS) association and beam alignment, we propose a lightweight online learning framework by embracing sparse representation (SR) and Gaussian process (GP). To obtain preliminary information of the transmission environment, fingerprint-based method is advocated for static scenarios, while its performance degrades in dynamic scenarios. To incorporate the influence of vehicle motion, we innovatively propose the idea of trajectory-aware fingerprint, which further triggers the following two designs: 1) Trajectory Prediction: We utilize GP to predict the trajectory of moving vehicles. Noticing the utility of the forecast information drops fast with the computational complexity, we propose a differentiated prediction framework to balance accuracy and model complexity to maximize such utility and 2) Fingerprint Adaptation: As the existence of infinite number of trajectories, we approximate a trajectory using grayscale image, and prove the influence of such approximation on throughput is limited. Then, given a predicted trajectory, SR is invoked to perform robust fingerprint adaptation that facilitating resource management. Finally, the simulation results demonstrate the superiority of the proposed framework.

Content popularity forecast is a key enabler toward the realization of proactive content caching, contributing to significant reduction of content fetching delay. Different from most of the existing literature that concentrating on enhancing the forecast accuracy, we tailor the popularity forecast and user clustering algorithms for improving the caching performance. Specifically, through analyzing the caching performance drop incurred by inaccurate popularity forecast from the Bayesian perspective, we obtain two critical insights, which trigger the following designs: 1) as the utility of forecast varies according to the content rank, we propose a content-caching-oriented popularity forecast algorithm based on Gaussian process (GP), where more computational resource is allocated to forecast the popularity of prioritized contents and 2) to alleviate the influence of forecast error on the rank of prioritized contents, we propose a content-caching-oriented user clustering algorithm based on the K-means algorithm. Since the involved optimization problem is NP-hard, we propose an iterative algorithm, whose convergence property in terms of region stability is proved, as the objective function may vary before a local minima is reached. Finally, the simulation results demonstrate the superiority of the proposed framework.

Electrostatic discharge (ESD) is a process in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the object within a very short period of time [1–2]. When a microchip or electronic system is subject to an ESD event, the huge ESD-induced current can likely damage the microchip and cause malfunction to the electronic system if the heat generated in the object cannot be dissipated quickly enough. It is estimated that about 35% of all damaged microchips are ESD related, resulting in a revenue loss of several hundred million dollars in the global semiconductor industry every year [3]. The continuing diminishing in the size of MOS devices makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical component to the successful development of the CMOS-based integrated circuits [4–7].

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a comprehensive computer-aided design tool for ESD applications. Specifically, the authors develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. The key components relevant to ESD in the MOS model are studied and the implementation procedure is discussed. Experimental data measured from the human body model tester are included in support of the model.

A practical approach of extracting MOS device BSIM3 model parameters to represent process variations is presented. Based on this approach, the performance spread of an MOS digital circuit can be predicted. The extraction scheme uses only end-of-line data so no extra measurements are needed. By integrating the model with routine data from the fabrication line, the statistical model can be built efficiently and updated frequently to reflect process changes. The developed statistical model is applied to the 0.25 /spl mu/m technology and verified on a 501-stage ring oscillator circuit.

Electrostatic discharges (ESDs) are everywhere-in our homes and businesses. Even the manufacturers of the electronics experience ESD failures in their factories. Electronic devices are sensitive to ESD. ESD results in failure of our computers, calculators, and car phones. There are ways to protect these sensitive components. This paper looks at ESD protection from a two-pronged approach: reducing the likelihood of having an ESD event and improving the robustness of the devices themselves. The first approach focuses on reducing the amount of charge that is developed and controlling the redistribution of any charges that are developed The second approach reviews ways to improve the circuit robustness by improving individual circuit elements and by adding additional elements for charge flow control and voltage clamping.

Electrostatic discharge (ESD) is an event that sends current through an integrated circuit (IC). This paper reviews the impact of ESD on the IC industry and details the four stages of an ESD event: (1) charge generation, (2) charge transfer, (3) device response, and (4) device failure. Topics reviewed are charge generation mechanisms, models for ESD charge transfer, electrical conduction mechanisms, and device damage mechanisms leading to circuit failure.

Junction field-effect transistor (JFET) circuit simulation using an existing physics-based JFET model is presented. This improved model has more predictive capability than the conventional JFET model employed in SPICE. Furthermore, it treats the linear and saturation regions in a unified manner and includes the subthreshold behavior, an effect not accounted for in the conventional model. The improved model is implemented into PSPICE run on a Sun workstation, and steady-state and transient responses are simulated for a JFET switching circuit and a JFET voltage follower circuit. Results obtained from the improved model compare favorably with that obtained from a two-dimensional device simulator PISCES and from measurements. For JFETs operating outside the subthreshold region, the conventional model with optimized parameters (extracted from measurements) also shows good accuracy. However, large discrepancies arise from the conventional model if JFETs are biased in the subthreshold region or if default model parameters are used.>

A computer-aided design tool for testing MOSFET integrated circuit performance as functions of MOSFET channel length and channel width variations is presented. The numerical model, which is developed based on the Tellegen's theorem and a database that contains the statistical information of MOSFET process parameters, is implemented in SPICE2 circuit simulator. Sensitivity simulation of a MOSFET operational amplifier is carried out to illustrate the usefulness of the present work.>

The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.>

The modeling of capacitance of p-n junction space-charge layers in semiconductor devices is discussed. First, previously developed models and methods are reviewed. Capacitance models developed recently by the authors that include mobile-carrier, nonquasi static, and multidimensional effects are then considered. These models yield more accurate device and circuit simulations for semiconductor integrated circuits. The emphasis is on diodes and bipolar transistors, but many concepts used apply as well to p-n junctions of metal-oxide-semiconductor field effect transistors. The review includes conventional homojunction devices (devices fabricated with a single semiconductor such as silicon) and the increasingly important heterojunction devices (devices fabricated with two or more semiconductors or a semiconductor having a spatially varying chemical composition such as gallium-aluminum-arsenide).>