A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical register file can be slow, particularly in the context of a wide-issue processor which requires an even larger physical register file, and many read and write ports. Previous work has suggested that a register cache can be used to address this problem. This paper proposes a new register caching mechanism in which a number of good features from previous approaches are combined with existing out-of-order processor hardware to implement a register cache for a large logical register file. It does so by separating the logical register file from the physical register file and using a modified form of register renaming to make the cache easy to implement. The physical register file in this configuration contains fewer entries than the logical register file and is designed so that the physical register file acts as a cache for the logical register file, which is the backing store. The tag information in this caching technique is kept in the register alias table and the physical register file. It is found that the caching mechanism improves IPC up to 20 % over an un-cached large logical register file and has performance near to that of a logical register file that is both large and fast. 1.

Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot always prove that a value is free of aliases, and thus promotion cannot always be applied. This paper proposes a new hardware structure, the store-load address table (SLAT), which watches both load and store instructions to see if they conflict with entries loaded into the SLAT by explicit software mapping instructions. One use of the SLAT is to allow values to be promoted to registers when they cannot be proven to be promotable by conventional compiler analysis. We call this new optimization speculative register promotion. Using this technique, a value can be promoted to a register and aliased loads and stores to that value's home memory location are caught and the proper fixup is performed. This paper will: a) describe the SLAT hardware and software; b) demonstrate that conventional register promotion is often inhibited by static compiler analysis; c) describe the speculative register promotion optimization; and d) quantify the performance increases possible when a SLAT is used. Our results show that for certain benchmarks, up to 35% of loads and 15% of stores can potentially be eliminated by using the SLAT.

As conventional board designs continue to decrease in size, the cost of "test" is rising proportionally relative to physical, bed-of-nails access. The purpose of this paper is to provide a generalized framework by which users can more quantitatively analyze the costs and benefits of removing physical test access from conventional, surface mount technology (SMT) boards for the purpose of bed-of-nails testing.

Boundary-Scan 1149.1 and its tight coupling with built-in self test (BIST) has proven to be an integral part in the time-to-market (TTM) and customer satisfaction that NCR computers are experiencing in their product realization cycles. As one of the many benefactors of these designed-in test features, the manufacturing test group within Columbia has realized tremendous increases in efficiencies in delivering tested modules, especially prototypes, to the respective design centers.>