With a suitable treatment of the exponents in the input operands, a hardware implementation of the Mactaggart and Jack fixed-point complex multiplication algorithm can also calculate a floating-point product with no loss in accuracy from the greater dynamic range of the floating-point inputs. This floating-point technique can be extended to any sum to two products operation, such as encountered in matrix multiplication and vector cross-products.>

A VLSI implementation of a bit-serial systolic architecture for a DFT processor has been developed which performs residue number system (RNS) processing over the ring of Gaussian integers. An architecture for a 128-point DFT using the chirp z-transform algorithm is described, and its use in an R2FFT architecture to obtain a 16,384-point transform is illustrated. Based on three custom-designed chips, the processor is capable of transforming data at a continuous 2 MHz rate. The use of RNS techniques and systolic arrays provides two dimensions of parallelism, resulting in hardware of low complexity and high speed. The overall system has great flexibility in dynamic range, and can be used in many signal processing applications.