This paper addresses the problem of layout automation of datapath cells. It presents an analytical approach to transistor placement under full custom design style and demonstrates that it can be applied to practical datapath designs. The presented approach is based on a mathematical model which employs a mixed integer linear programming technique. The placement algorithm adopts the custom design techniques commonly used by datapath layout designers in generating hand-crafted designs. An important aspect of the presented method is the efficient management of the complexity of the underlying mathematical model which makes it applicable to real designs. The authors implemented the presented datapath design technique as an experimental software tool running in the industrial environment. The generated layout results are competitive with manual designs provided by experienced layout designers.

A description is given of CLEO, an automatic CMOS layout generator that takes as input an arbitrary sized circuit schematic and produces a CMOS layout as one or more horizontal rows of vertically oriented transistors. The layout can be controlled by specifying geometric constraints such as the number of rows desired, their specific heights and widths, and pins located on the region boundary. The tool was designed to lay out random logic sections of custom CMOS chips and is typically used with circuits ranging between 25 and 500 logic gates. CLEO obtains density close to handcrafted layout.>