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Klinton Remedios

dblp:05/5370 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 67% Integrated circuit design · 33%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › pattern matching accelerator
string matching accelerator
0.011995
CASM: A VLSI Chip for Approximate String Matching · IEEE Trans. Pattern Anal. Mach. Intell. 1995
Hardware accelerators and domain-specific architectures
systolic array
0.011995
CASM: A VLSI Chip for Approximate String Matching · IEEE Trans. Pattern Anal. Mach. Intell. 1995
Integrated circuit design › digital circuit design
VLSI architecture
0.011995
CASM: A VLSI Chip for Approximate String Matching · IEEE Trans. Pattern Anal. Mach. Intell. 1995
Algorithms and data structures › sequence algorithms › string algorithms › string matching
approximate string matching
0.011995
CASM: A VLSI Chip for Approximate String Matching · IEEE Trans. Pattern Anal. Mach. Intell. 1995
Algorithms and data structures › sequence algorithms
string algorithms
0.011995
CASM: A VLSI Chip for Approximate String Matching · IEEE Trans. Pattern Anal. Mach. Intell. 1995

Methods — techniques the papers use, named apart from their topics

edit distance · 0.0dynamic programming · 0.0
YearPublicationVenuePosition
1995 CASM: A VLSI Chip for Approximate String Matching
abstract
The edit distance between two strings a1, ..., a/sub m/ and b/sub 1/, ..., b/sub n/ is the minimum cost s of a sequence of editing operations (insertions, deletions and substitutions) that convert one string into the other. This paper describes the design and implementation of a linear systolic array chip for computing the edit distance between two strings over a given alphabet. An encoding scheme is proposed which reduces the number of bits required to represent a state in the computation. The architecture is a parallel realization of the standard dynamic programming algorithm proposed by Wagner and Fischer (1974), and can perform approximate string matching for variable edit costs. More importantly, the architecture does not place any constraint on the lengths of the strings that can be compared. It makes use of simple basic cells and requires regular nearest neighbor communication, which makes it suitable for VLSI implementation. A prototype of this array has been built at the University of South Florida.>
Raghu Sastry, N. Ranganathan, Klinton Remedios
IEEE Trans. Pattern Anal. Mach. Intell.3