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R. Curtis Harting

dblp:05/5468 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 23% Interconnection networks and networks-on-chip · 23% Parallel and multicore computing · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel programming runtimes
active messages
0.212015
On-Chip Active Messages for Speed, Scalability, and Efficiency · IEEE Trans. Parallel Distributed Syst. 2015
Memory systems
cache coherence
0.212015
On-Chip Active Messages for Speed, Scalability, and Efficiency · IEEE Trans. Parallel Distributed Syst. 2015
Processor architecture and microarchitecture › many-core architecture
many-core chip multiprocessor
0.212015
On-Chip Active Messages for Speed, Scalability, and Efficiency · IEEE Trans. Parallel Distributed Syst. 2015
Interconnection networks and networks-on-chip
on-chip communication
0.212015
On-Chip Active Messages for Speed, Scalability, and Efficiency · IEEE Trans. Parallel Distributed Syst. 2015
Performance modeling and evaluation › parallel performance evaluation
multicore scalability
0.112015
On-Chip Active Messages for Speed, Scalability, and Efficiency · IEEE Trans. Parallel Distributed Syst. 2015

Methods — techniques the papers use, named apart from their topics

energy measurement · 0.2active message handler · 0.2
YearPublicationVenuePosition
2015 On-Chip Active Messages for Speed, Scalability, and Efficiency
abstract
This paper describes and quantifies the benefits of adding low-overhead active messages to many-core, cache-coherent chip-multiprocessors. The active messages we analyze are user defined and trigger the atomic execution of a custom software handler at the destination. Programmers can use these active messages to both move data with less overhead than cache coherency and, more importantly, explicitly send computation to data. Doing so greatly improves (11× speed, 4.8× energy) communication idioms such as shared object modification, reductions, data walks, point-to-point communication, and all-to-all communication. Active messages enhance program scalability: applications using them run 63 percent faster with 11 percent less energy on 256 cores. The relative benefits of active messages grow with larger numbers of cores.
R. Curtis Harting, William J. Dally
IEEE Trans. Parallel Distributed Syst.1
2011 The utility of fast active messages on many-core chips: Efficient supercomputing project
R. Curtis Harting, Vishal Parikh, William J. Dally
Hot Chips Symposium1