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Kuo-Rueih Ricky Pan

dblp:05/5844 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
boolean function decomposition
0.011996
OBDD-based function decomposition: algorithms and implementation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation › logic synthesis › technology mapping
FPGA technology mapping
0.011996
OBDD-based function decomposition: algorithms and implementation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996
Electronic design automation
logic synthesis
0.011996
OBDD-based function decomposition: algorithms and implementation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996

Methods — techniques the papers use, named apart from their topics

ordered binary decision diagrams · 0.0common subfunction identification · 0.0
YearPublicationVenuePosition
1996 OBDD-based function decomposition: algorithms and implementation
abstract
This paper presents algorithms for disjunctive and nondisjunctive decomposition of Boolean functions and Boolean methods for identifying common subfunctions from multiple Boolean functions. Ordered binary decision diagrams are used to represent and manipulate Boolean functions so that the proposed methods can be implemented concisely. These techniques are applied to the synthesis of look-up table based field programmable gate arrays and results are presented.
Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1994 FPGA Synthesis Using Function Decomposition
abstract
Presents two Boolean methods for identifying common subfunctions from multiple-output functions. The first method is based on encoding the distinct columns in the stacked decomposition chart of the multiple-output function; the second method is based on the examination and encoding of all possible subfunctions that can be generated from a function with respect to a given subset of input variables. We then apply these methods to the synthesis of lookup-table based field programmable gate arrays. Experimental results are very encouraging.>
Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram
ICCD2