With the significant advancement of statistical timing and yield analysis algorithms, there is a strong need for accurate and analytical spatial correlation models. In this paper, we propose a novel spatial correlation modeling method that can not only capture the general spatial correlation relationship but also can generate highly accurate and analytical models. Our method, based on singular value decomposition, can generate sequences of polynomial weighted by the singular values. Experimental results from foundry measurement data show that our proposed approach is 3x accuracy improvement over several distance based spatial correlation modeling methods.

With the significant advancement of statistical timing and yield analysis algorithms, there is a strong need for accurate and analytical spatial correlation models. In this paper, we propose a novel spatial correlation modeling method not only can capture the general spatial correlation relationship but also can generate highly accurate and analytical models. Our method, based on Singular Value Decomposition (SVD), can generate sequences of polynomial weighted by the singular values. Experimental results from foundry measurement data show that our proposed approach is 5X accuracy improvement over several distance based spatial correlation modeling methods.

As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the postlayout stage. The increasing design complexity, however, leaves very limited space for postlayout optimization. It is thus desirable to consider the double-via insertion at both the routing and postrouting stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework and features a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing). We also propose a graph-matching based post-layout double-via insertion algorithm to achieve a higher insertion rate. In particular, the algorithm is optimal for grid-based routing with up to three routing layers and the stacked-via structure. Experiments show that our methods significantly improve the via count, number of dead vias, double-via insertion rates, and running times.

As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the post-layout stage. The increasing design complexity, however, leaves very limited space for post-layout optimization. It is thus desirable to consider the double-via insertion at both routing and post-routing stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework. We also propose a new post-layout double-via insertion algorithm to achieve a higher insertion rate. Based on a bipartite graph matching formulation, we develop an optimal double-via insertion algorithm for the cases with up to three routing layers and the stack-via structure, and then extend the algorithm to handle the general cases. Experiments show that our methods significantly improve the via count, the number of dead vias, double-via insertion rates, and running times.