This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.

This paper presents new methods and experimental production test results from completely moving away from traditional fault methods towards using critical area based methods instead. The focus of this paper is on measuring the quality of test patterns not by measuring the test coverage but by measuring the covered or detected total critical area (TCA). This is the first time that a TCA for all defects in the digital logic part of a chip can be calculated. The paper will present TCA figures from defect extraction on interconnects outside of standard cells as well as for all defects inside standard cells. We also will present methods for extracting cell-neighborhood defects, their TCA and which of those defects are not covered by cell-aware and interconnect test patterns.

Stringent quality requirements in the automotive sector result in the necessity of targeting additional fault models beyond traditional stuck-at and transition. This paper is concerned with bridging faults, which are well known to require additional tests to detect those which are not detected by traditional tests. To keep ATPG tractable, bridging faults must be extracted from layout to obtain nodes which are physically close together. There are well established methods for such extraction but typically involve complex flows with several tools. This paper describes a much simpler approach using the same layout database that is used for layout-aware diagnosis. The extraction process automatically ranks bridges on critical area so it is simple to truncate the fault list, if necessary. Since each bridge has a critical area it is also possible to provide a weighted critical area based coverage, which is physically more realistic than a simple fault count. The paper describes experimental results, including coverage gains, critical area calculation, and explores physical versus traditional coverage metrics.

Volume diagnosis of scan fails is au effective method of identifying dominant defect mechanisms for yield improvement. However, traditional diagnosis is at the library cell level and identifies only interconnect defects and defective cells. In practice, many defects affect only the internal logic of cells, such as polysilicon contacts, but cannot be pinpointed, resulting in not identifying some potential yield limiters. This paper describes a solution to the problem by showing how diagnosis can be extended to internal cell defects. This is enabled by characterizing a cell library similar to what is needed for cell-aware ATPG, but including more information for diagnosis such as layout data. A flow is described to produce the characterization, which includes requirements for the cell views. Diagnosis results include layout marker files for cell internal suspects which can be viewed in a GDS newer and used to obtain X/Y coordinates to guide physical failure analysis. Successful implementation is demonstrated for a 160nm automotive product.

The European Test Symposium (ETS) Best Paper Award, which was introduced in 2004 when the European Test Workshop (ETW) turned into the ETS, aims to maintain and encourage the quality of papers and presentations in the ETS technical program.

Increasing process variations result in increasing statistical diversity in manufactured devices. Test plans that are developed without this diversity in mind are bound to result in poor test quality/yield and/or long test times. Adaptive testing is a general term that is used to tailor the test strategy to accommodate a wide range of variation in the statistical characteristics of manufactured devices. In this paper, we provide a review of the key works in both digital and analog domains.

Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.

This paper describes the development of adaptive test in response to the ever growing need to dynamically and cost effectively tailor IC testing to discriminately manage manufacturing process variations. Various degrees of adoption are presented, together with benefits and examples of it's use. Finally, challenges for future development are discussed.

This tutorial discusses test methods and voltage stress approaches required to ensure effective cost effective defect screening to produce high quality, reliable products. Wafer level reliability screens (WLRS) refers to the application of screens during wafer test that will both activate and detect a sufficient number of defects so that early life failure rate (ELFR) is reduced enough to meet customer spec, preferably without doing burn-in. Further, these screens have to have acceptable yield loss and acceptable test times.

This paper describes several different approaches to obtain test cost reduction, with emphasis on experimental results obtained for a class of ASICs, although the techniques are general. A review is given of some architectural approaches before giving details of techniques which address reduction in test time. The importance of the gathering and analysis of production data is highlighted with a view to better balance wafer and package tests, eliminate ineffective tests, truncate existing tests and carefully examine at which voltage a test should be run. Stress testing is also discussed with the goal of optimizing tests which are run before and after stress.

This paper discusses aspects which have to be considered in order to conduct a successful test experiment. Emphasis is on using data collected from testing large numbers of parts. Statistical arguments are presented relating to making meaningful conclusions, which includes the effects of sample size. Several pitfalls that can corrupt or skew data are discussed, and the importance of unambiguous presentation of data and results is stressed

This paper presents the results of an extensive data collection study where production wafer and package test data are examined from the point of view of determining an optimal mix of wafer and package tests to achieve the combined goals of high defect coverage and rapid yield learning, while simultaneously examining the possibility of using lower cost ATE. Results for at-speed tests show that for some types of parts reduced speed transition fault testing can be very effective.

This paper describes an experimental study to understand issues and requirements for structural-based testing using low cost testers, compared to functional-based testing using expensive testers. Several studies have been directed at the effectiveness of various test methods, but none explicitly addressed issues involved in attempting to replace functional vectors with scan vectors and none carried the experiment further by placing defective chips into systems and running system tests. This paper describes the results of such an experiment and offers insight into necessary requirements for reduction or elimination of functional tests.

The use of a single pass/fail threshold for IDDQ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describes a method of using "current signatures" which uses only simple comparisons on the tester, and which automatically scales with process variations which give a wide range of background currents. Dynamic thresholds are used, based on the ratio of maximum to minimum current. Using a single IDDQ measurement for each die, upper and lower comparator values are set, against which IDDQ for each vector in the suite is compared. Production data is presented to verify the validity of the method.

The distortion of test coverage statistics by overly simplistic circuit and fault models is explored. It is shown that the artificially high single stuck-at coverage reported on traditional gate-level models results in the omission of test patterns essential to achieve full coverage. The problem lies not directly with the fault model, but instead with the gate models and test generator assumptions used. The necessity of two-pattern tests is demonstrated on simple library cells, and the stuck-at coverage improvement measured on benchmark circuits is shown to average 33%. The need for a superior fault model is explained.

The use of a single pass/fail threshold for I/sub DDQ/ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describes a method of using "current signatures" which uses only simple comparisons on the tester, and which automatically scales with process variations which give a wide range of background currents. Dynamic thresholds are used, based on the ratio of maximum to minimum current. Using a single I/sub DDQ/ measurement for each die, upper and lower comparator values are set, against which I/sub DDQ/ for each vector in the suite is compared. Production data is presented to verify the validity of the method.

This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifies transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the size of these transistors and various process parameters in order to calculate the actual I/sub DDQ/ value. SPICE simulation results are presented on a variety of circuits to both calibrate the simulator, and to demonstrate state, time and sequence dependencies of circuits. Some preliminary results are also given for an actual production chip.

Sensitive I/sub DDQ/ and LVMF (low V/sub DD/, maximum frequency) tests were done to examine reliability indicators and burn-in economics for CMOS ICs. These experiments used 3,495 CMOS 1 Mb SRAMs for special I/sub DDQ/ tests, LVMF tests, burn-in and life tests, and failure analysis. I/sub DDQ/ was measured at the maximum V/sub DD/ tolerated by the IC, ranging from 40% to 60% above the nominal V/sub DD/. These data indicate that elevated voltage I/sub DDQ/ screening can replace burn-in for CMOS ICs, including ICs from poor quality (rogue or maverick) lots. A low reliability risk group (27% of the population) that failed only I/sub DDQ/ tests was identified by I/sub DDQ/ signatures and life tests. Two other defect classes were examined for this yield reclamation potential for ICs that failed only I/sub DDQ/ tests.

The SEMATECH "Test Methods Evaluation" study, Project Number S-121, is an experiment to determine the relative merits of several test methodologies often used by SEMATECH member companies and other IC manufacturers. Conclusions drawn from the experiment thus far have indicated that each test methodology uniquely detects defects. This experimentation and analysis would not have been possible outside a consortium setting such as SEMATECH. Its conclusions may affect other major segments of the industry, including ATE manufacturers, CAD vendors, and academia. This paper gives a brief overview of the experiment and summarizes its findings.

This paper describes an experiment in which various semiconductor test methodologies (stuck-fault, functional, delay and IDDq) are applied to an ASIC device. The goal of this project is to provide the data that will enable manufacturers to optimize their application of the various tests. This project was supported through SEMATECH (Project S-121, "Semiconductor Test Method Evaluation ").

This paper investigates the relative effectiveness of scan-based AC tests, IDDQ tests and functional tests for the detection of defective chips, particularly those exhibiting delay faults. Data are presented from an experiment in which a production ASIC was tested with a number of scan and functional tests, together with IDDQ. Results show that all tests detect unique failures, indicating the presence of additional unmodelled faults. The effectiveness of the AC tests shows that targeting additional faults produces better quality than relying on peripheral coverage of existing tests.

One of the problems of the use of the term "test synthesis" is that it is so general that almost any aspect of test automation can be claimed to fall under its umbrella. Because of the popularity of the term, and the unpopularity (particularly with CAD vendors) of having a system which does NQT carry out test synthesis, it is tempting to interpret the term as something equivalent to "synthesizing something to do with test". Thus, an ATPG tool which automatically substitutes scan cells and connects up scan chains to a previously synthesized design can be legitimately claimed to be carrying out test synthesis. This is markedly different to a tool which inserts HDL code for BIST circuitry into the overall high level description of a design. The spirit of high level test synthesis is encapsulated in a one-pass system. Certain components are easily identifiable, for example the addition of separate circuitry like BIST controllers or TAP controllers for boundary scan. Such circuitry can be specified as HDL code and relatively easily-made to conform to design rules. For random logic, however, there needs to be a convenient way of building in necessary constraints to ensure tester-applicable patterns can be generated. To have tests which target non-stuck-at faults and which are completely automatically generated means paying attention to both additional constraints during design synthesis and better ATPG systems.

An unresolved issue in IC testing is what mix of coverages of different types of test is required in order to achieve a given quality goal. This paper investigates the interaction between IDDQ and stuck-at coverage and examines the use of IDDQ to increase effective stuck-at coverage, particularly in situations where the graded coverage is lower than the desired goal. Empirical data is presented which examines the extent to which a varying number of IDDQ tests can detect parts which would fail stuck-at tests. This leads to development of a composite metric, based on stuck-at coverage, which allows a tradeoff to be made between adding further logic tests and adding IDDQ tests.

This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. In particular, the issue of nonuniform distribution of detected faults is addressed, It is shown that when any degree of defect clustering occurs in the IC fabrication process, there is a very big difference in final quality between covering the chip evenly all over and leaving parts relatively untested, even if the coverage is the same in both cases. Empirical evidence is given to support the theory.>

This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. The first part addresses the issue of non-uniform distribution of detected faults. It is shown that there is a large difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases. The second part deals with the use of weighted, rather than unweighted fault coverages and investigates the use of readily-available extracted capacitance information to produce a weighted fault coverage which is more useful for producing quality estimates, without having to perform a full defect analysis. Results show significant differences in weighted versus unweighted coverages, and also that these differences can be in either direction.

This paper addresses the issue of non-uniform distribution of detected faults. It is shown that there is a very big difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases.>

The motivation for carrying out fault grading is to obtain a metric which expresses the effectiveness of a test in screening defective components. In terms of shipped parts, this effectiveness is reflected by the reject rate, or the proportion of parts which fail when used in their intended application. The most useful metric would be one which tracks the resultant quality level well, so that improving the metric would result in fewer shipped bad die, and a "perfect" score would result in zero reject rate.>

In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults.>

This paper discusses the use of stuck-at fault coverage as a means of determining quality levels. Data from a part tested with both functional and scan tests is analyzed and compared to three existing theories. It is shown that reasonable predictions of quality level are possible for the functional tests, but that scan tests produce significantly worse quality levels than predicted, Apparent clustering of defects resulted in very good quality levels for fault coverages less than 99%.

Signature analysis is an accepted method of obtaining data compression for built-in testing applications. The author deals with a unified approach to the analysis of multiple-input signature analyzers by considering them as finite state switching circuits. This approach is used to investigate and compare different implementations, and it is shown that there is a large range of alternatives to achieve a given characteristic polynomial. Particular emphasis is placed on the two most common implementations. It is shown that both perform polynomial division, with each input of one circuit being equivalent to a combination of inputs of the other. The approach also gives a method of expressing aliasing patterns for both implementations, which leads to a study of the differences with regard to certain error detection capabilities.>

In a recent paper, Hannington and Whitehead1describe the design of a floating point digital differential analyzer (DDA). There are, however, shortcomings in the design which we will describe in this correspondence.

This correspondence shows that when solving differential equations of the form ẏ = Σanyn, DDA's that perform trapezoidal integration for linear equations cannot be directly employed. Modified register transfers are developed for the representative example of ẏ = y2, and results are presented for both accurate numerical solutions and curve generation on a graphic display.