Demo Data from EDBT 2026 / reviewers in the wild / expert
Robert Lindell
dblp:05/647
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Security and privacy · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 89% Hardware reliability and fault tolerance · 11% | |
| Network and information security
2 papers |
Hardware security and side channels · 50% Systems and software security · 50% |
Topics — the 3 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Systems and software security › memory protection
hardware-supported protection |
0.0 | 1 | 1996 | An Analysis of the Intel 80x86 Security Architecture and Implementations · IEEE Trans. Software Eng. 1996 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 1 | 1995 | The Intel 80×86 processor architecture: pitfalls for secure systems · S&P 1995 |
Processor architecture and microarchitecture › instruction set architecture › CISC
x86 |
0.0 | 1 | 1995 | The Intel 80×86 processor architecture: pitfalls for secure systems · S&P 1995 |
Methods — techniques the papers use, named apart from their topics
architectural analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | An Analysis of the Intel 80x86 Security Architecture and ImplementationsabstractAn in depth analysis of the 80/spl times/86 processor families identifies architectural properties that may have unexpected, and undesirable, results in secure computer systems. In addition, reported implementation errors in some processor versions render them undesirable for secure systems because of potential security and reliability problems. We discuss the imbalance in scrutiny for hardware protection mechanisms relative to software, and why this imbalance is increasingly difficult to justify as hardware complexity increases. We illustrate this difficulty with examples of architectural subtleties and reported implementation errors. Olin Sibert, Phillip A. Porras, Robert Lindell |
IEEE Trans. Software Eng. | 3 |
| 1995 | The Intel 80×86 processor architecture: pitfalls for secure systemsabstractAn in-depth analysis of the 80/spl times/86 processor families identifies architectural properties that may have unexpected, and undesirable, results in secure computer systems. In addition, reported implementation errors in some processor versions render them undesirable for secure systems because of potential security and reliability problems. We discuss the imbalance in scrutiny for hardware protection mechanisms relative to software, and why this imbalance is increasingly difficult to justify as hardware complexity increases. We illustrate this difficulty with examples of architectural subtleties and reported implementation errors.> Olin Sibert, Phillip A. Porras, Robert Lindell |
S&P | 3 |
| 1986 | Name Service Locality and Cache Design in a Distributed Operating System
Alan B. Sheltzer, Robert Lindell, Gerald J. Popek |
ICDCS | 2 |