This paper presents an overview of the Internet of Things (IoT) device design and simulation, with a specific focus on low-power design principles - everything in the context of the LoLiPoP-IoT project. The project aims to enhance IoT device usability by reducing maintenance requirements related to battery recharging or replacement. Another key goal is to significantly decrease the massive waste generated by discarded primary batteries, contributing to more sustainable and user-friendly IoT solutions for the future. The primary focus of this paper is on a custom IoT localization tag, for which we simulate solar cells - ranging from basic modeling to their integration into electrical circuits - and the power consumption of the tag's electronics platform. The analyzed sample platform is built on the nRF52833 microcontroller and the DW3110 ultra-wideband transceiver. We also applied our experimental framework principles to optimize power consumption and extend battery life. Reductions in photovoltaic panel area were achieved for both devices with a 5-year lifespan and fully autonomous tags, though with increased localization latency. Furthermore, this paper demonstrates how IoT devices, including their firmware, can be effectively modeled and simulated using publicly available tools.

The increasing interest in IoT devices poses significant challenges in battery waste, not to mention the effort needed to replace the batteries in remote applications. In the LoLiPoPIoT project, we address these issues by developing energy-efficient IoT platforms that extend the device’s battery life through lowpower design and energy harvesting. However, for a successful design, preliminary measurements and simulations need to be done to demonstrate the feasibility of the utilized technologies and their dimensioning. This paper presents a method of collecting data and creating a novel portable simulation model implemented in a Microsoft Excel spreadsheet. During the data collection phase, we plot detailed energy consumption and income of our device (i.e., asset tracking tag). PC1D simulations of a crystalline-silicon photo-voltaic panel and the device model were utilized to collect data for the final (i.e., composed) model. Our model allows real-time adjustments of key parameters, such as ambient light intensity, battery capacity, and photo-voltaic panel sizing. Our goal is to deliver a solution that allows our partner to conduct basic experiments on their own computers with a user-friendly interface for parameter selection and result visualization. Our results indicate that for one application area, a $25 \mathrm{~cm}^{2}$ photovoltaic panel is needed, while for the other, a $23 \mathrm{~cm}^{2}$ panel is enough.

The LoLiPoP-IoT project aims to pioneer Long Life Power Platforms for IoT to extend battery life, minimize maintenance, and facilitate installation within existing environments. With a focus on supporting an inclusive ecosystem of developers, integrators, coordinators, and users, the project's Grand Objectives encompass a range of aims, including providing long-lasting battery solutions, reducing battery waste, enhancing asset tracking and predictive maintenance, and improving energy efficiency in buildings. These objectives are realized through nine selected practical applications across three primary domains: Asset Tracking, Condition Monitoring and Predictive Maintenance, and Energy Efficiency and Comfort in Buildings. Expected impacts of the LoLiPoP-IoT project include significantly extended battery life, reduced maintenance overhead, decreased costs associated with asset location, improved asset management efficiency, enhanced building comfort with reduced energy consumption, and substantial revenue generation for industry partners. The project's strategic objectives are notably harmonized with key EU initiatives outlined in the Green Deal, Circular Economy, and the New Industrial Strategy for Europe.

The concept of polymorphic electronics allows to efficiently implement two or more functions in a single circuit, whereas the currently selected function depends on the state of the circuit operating environment. The key components of such circuits are polymorphic gates. Since the introduction of polymorphic electronics, a few tens of polymorphic gates have been published. However, a large number of them exhibit parameters that fall behind ubiquitous CMOS technology. As a result of that, the perspective of their utilization for real applications becomes rather bleak. This paper shows a new approach to polymorphic electronics. It is based on gates whose behavior depends on the polarity of dedicated power supply rails. Such an approach allows to design of gates with significantly improved parameters. Several sets of bi-functional polymorphic gates were designed and validated by HSPICE simulations. The advantage of newly designed gates is demonstrated at two higher levels of abstraction - bi-functional RTL components and applications (bi-functional image filters). Both designed RTL components and image filters showed to be significantly area-efficient compared to the best-known solutions.

The concept of polymorphic electronics allows to efficiently implement two or more functions in a single circuit. It is characteristic of that approach that the currently selected function from the set of available ones depends on the state of the circuit operating environment. The key components of such circuits are polymorphic gates. Since the introduction of polymorphic electronics, just a few tens of polymorphic gates have been published. However, a large number of them exhibit parameters that fall behind ubiquitous CMOS technology, which makes their utilization for real applications rather difficult. As it turns out, the synthesis of polymorphic circuits achieves a significantly higher degree of complexity in comparison to the ordinary digital circuit. In past, many of the previously reported polymorphic circuits were designed using evolutionary principles (EA, CGP, etc.). It has been shown that the problem of scalable synthesis techniques suitable for large-scale polymorphic circuits could be addressed by the adoption of multi-level synthesis techniques such as And-Inverter-Graphs. The PAIG (Polymorphic And-Inverter-Graphs) concept and synthesis techniques based on it seem to be a promising approach. This paper shows how modern polymorphic gates could be used in combination with a PAIG-based synthesis tool to obtain an efficient implementation of complex polymorphic circuits.

The synthesis process of complex polymorphic circuits represents a very demanding task in which the existing approaches, frequently based on various techniques known from the conventional digital circuits domain, fail to deliver acceptable results. This fact initiated the development of a scalable, rigid and multilevel-oriented synthesis flow to tackle the existing shortcomings. However, the conducted experiments have revealed a need to carry out certain modifications to improve the efficiency of the initially proposed polymorphic circuits optimization concept. Therefore, the main attention in this article is given to the investigation of KL-cuts and their impact on the resulting circuitry structure produced by the polymorphic and-inverter graphs rewriting technique introduced earlier. The principle of using KL-cuts within the synthesis process will be explained. Besides, a discussion of the obtained results and their comparison with the previously reported approach will be provided for a better clarification of the potential benefits.

One of the possible ways how to accomplish multifunctional digital circuits follows the paradigm of Polymorphic electronics. Design of such circuits is closely related to the availability of suitable polymorphic gates. Unfortunately, the actual electronic properties of the polymorphic gates published in the past were way too far from matching their conventional CMOS counterparts. A new type of polymorphic gates with significantly better parameters has been recently shown: Gates whose function is determined by the polarity of dedicated supply rails. Such gates have been investigated mostly in terms of their size and propagation delay. In this paper, power consumption of exactly such gates is being analysed. That makes it possible to identify the best variants among them and subsequently compare their properties with conventional CMOS circuits. Furthermore, an extensive gate set consisting of individual polymorphic gates with the lowest power consumption was introduced together with a gate set demonstrating the best found trade-off between gate size, delay and power consumption. Both sets are integrated now into the PoLibSi library - freely available library with polymorphic gates of the new generation.

Main objective of this paper is to introduce a novel methodology for scalable synthesis of multifunctional (polymorphic) digital circuits. Despite the fact that several approaches have been proposed during recent years, those are applicable for small-scale circuits only or based on various evolution-inspired techniques. Obvious, there does not exist yet scalable synthesis methodology for complex multifunctional circuits. The proposed methodology is based on And-Inverter Graphs (AIGs) with built-in extension for multifunctional circuits where the employment of rewriting techniques reduces the area by sharing common resources of two different input circuits. Experiments performed on publicly available benchmark circuits demonstrate significant area reduction.

One of the main research directions of polymorphic electronics is focused on various issues connected with the design of basic polymorphic components - polymorphic gates. Without a sufficient amount of polymorphic gates offering good properties, conventional electronics will be most likely the preferred way before polymorphic electronics in application scenarios targeting multifunctional behaviour or reconfiguration. The main objective of this paper is to propose a library called PoLibSi which contains eight sets of efficient bi-functional two-input polymorphic gates, whose function is selected by mutual polarity of dedicated power rails. The gate sets differ in the transistor type (conventional MOSFET, emerging double-gate ambipolar transistors), feature the gate sets were optimized to (transistor count, delay, power consumption) and input impedance constraint. The individual gates were designed by means of using an evolutionary based approach and further validated by HSPICE simulations. Each gate implementation includes a schematic, HSPICE description and simulation results. Moreover, propagation delay and power consumption is provided for all MOSFET based gates. Furthermore, each gate set is complete - it provides efficient implementation of any pair of two-input Boolean functions. Besides providing polymorphic gates with better properties to the research society, the aim of the proposed library is to improve the synthesis of polymorphic circuits in terms of the resulting size, as it is also shown in the paper. Finally, the PoLibSi library is available at: www.fit.vutbr.cz/~inevoral/polibsi.

Ambipolarity, a unique feature typically found in some beyond silicon devices, e.g. CNT or organic FETs, is still treated today just as something rather peculiar. But in reality, it does not hinder such devices from utilization when it comes to the implementation of logic. From other point of view, this feature could be perceived as an opportunity to implement the logic in more refined and efficient way. The practical impact of ambipolarity results in devices which becomes more versatile than conventional FET element. In this paper, a set of multifunctional logic gates based on ambipolar FETs is presented. The multifunctionality of these gates means that each gate could exhibit one of two defined functions in a given moment. The selection of their function depends on circumstances under which the circuit is operated. The proposed set of gates could be employed in multifunctional circuits using techniques and procedures established for polymorphic electronics. This field of study, yet proposed nearly 20 years ago, now offers synthesis methods and application approaches to obtain an efficient implementation of more than one function in one logic circuit.

Physical radiation experiments are a vital means for calibrating simulation models targeted to studying the impact of ionizing particles on VLSI circuits. However, their conduction requires special care and a very specific setup. In this paper we give an overview of such an experimental setup, and highlight some specific details. Beyond showing the context overarching the objectives of the experiments, the envisioned radiation sources, as well as design and architecture of a specific target ASIC, we will put specific emphasis on the communication infrastructure, namely an FPGA that controls the data exchange between some preprocessing infrastructure located on the target ASIC on one side and the host PC running the data analysis on the other. Finally, the physical arrangement comprising carrier PCB for the target ASIC, and cabling, which need to adhere specific requirements, will receive some attention as well.

The fundamental aspect behind this paper is focused on behaviour of polymorphic digital circuits in potentially harsh operating environment. The area of polymorphic electronics takes and an advantage of inherently built-in features that open up the possibility for on-the-fly adjustment of a particular circuit function with respect to the environment. The most prevalent benefit here is connected with the fact that space-efficient circuit implementation can be achieved due to the adoption of polymorphic principles and, thus, eliminate the need for an additional function change controller. The experimental setup was based around reconfigurable polymorphic chip REPOMO32, which is primarily designed to be configured (in addition to the configuration bit stream) by means of using the level of power supply voltage (Vdd), and carrier board with all necessary capabilities for temperature measurement up to -40C boundary and its response analysis. Experiments clearly indicate that polymorphic gates in the chip can be easily controlled not only by Vdd, but also by temperature. The obtained results also prove that the physical design of the REPOMO32 chip is robust enough under wide range f operating temperature.

The paper describes a series of experiments performed with the aim to analyze the fundamental impact of high temperatures on behavior of polymorphic digital circuits. These experiments were conducted using a reconfigurable polymorphic chip REPOMO32 which is configured (in addition to the configuration bit stream) using the level of power supply voltage (Vdd). Experiments show that polymorphic gates in the chip can be easily involved (in terms of functionality) not only by Vdd, but also by temperature. Because experiments also prove that the physical design of the REPOMO32 chip is robust enough to keep the functionality of all circuitry of the REPOMO32 and its dynamic parameters are stable enough under wide range of operating temperature, the chip can also be used for future designs of digital polymorphic circuits controlled by temperature.

The paper presents a new design approach to digital circuits that provides for an increased chip operation reliability from temperature point of view. The key aspect behind the proposed method of approach is to avoid chip overheating due to special design and subsequent integration of dedicated circuit controller. Such element is blended seamlessly with the surrounding circuitry and posses the ability to reconfigure itself when the temperature of the chip goes beyond defined temperature boundary. After the end of reconfiguration phase, the controller ensures only indispensable function. By this arrangement, the power and heat dissipation of the circuit is reduced until the chip temperature falls again under certain level. When the chip is cooled down appropriately, the controller returns back to normal operating mode automatically. The proposed approach utilises principles of polymorphic digital circuits which embrace smart and fast reconfiguration, compact and cost-effective design with embedded sensors, where the aim is to ensure overall system stability and in the same time increase its dependability.

The paper describes a reconfigurable polymorphic chip REPOMO32, experiments carried out with this chip and provides report on important experiences with regard to practical applications of digital polymorphic circuits sensitive to the power supply voltage (Vdd). REPOMO32 contains array of 32 configurable logic elements which can perform polymorphic NAND/NOR function controlled by the level of the Vdd. Moreover, it can be declared as the first fabricated chip of this kind which basically allows the user to design more complex circuits than only a few gates.

Main objective of this paper is to outline possible ways how to achieve a substantial acceleration in case of advection-diffusion equation (A-DE) calculation, which is commonly used for a description of the pollutant behavior in atmosphere. A-DE is a land of partial differential equation (PDE) and in general case it is usually solved by numerical integration due to its high complexity. These types of calculations are time consuming thus the main idea of our work is to adopt compute unified device architecture (CUDA) software framework and commodity add-on card with general-purpose graphics processing unit (GPU) to do the calculations in a faster way. The solution is based on method of lines with 4 order Runge-Kutta scheme to handle the integration. As a matter of fact, the selected approach involves number of auxiliary variables and thus the memory management is critical in order to achieve desired performance. From a technical point of view, we have implemented a particular variant of the A-DE system, where the pollutant concentration is time-dependent. An efficient data handling is primarily based on the exploitation of shared memory blocks and texture caches inside GPU chip. Detailed evaluation of the obtained results is given in this paper where an astonishing execution speed up of GPU-based solution is demonstrated in comparison to standard CPU.