For nanometer design, conventional timing analysis may generate over-optimistic results on criticality-dependent paths. A late arrival time at the data input of a flip-flop lengthens the propagation delay from the clock pin to the data output of this flip-flop, thus degrading the timing margins of paths launching from this flip-flop. To remove the optimism, in this paper, we first propose a simple yet effective triangle model to characterize the criticality-dependency effect. Then, we devise a novel criticality-dependency-aware timing analysis flow, which is seamlessly integrated with the common static timing analysis flow. Experimental results show that our approach can effectively analyze the criticality-dependency effect: Based on the proposed triangle model, we can accurately identify all timing-risky flip-flops and capture the induced timing margin degradation.

To achieve timing closure, performance-driven optimizations are repeatedly performed throughout the modern IC design flow. Along with these optimization operations, how to incrementally update timing information efficiently and accurately becomes a crucial task for fast turnaround time. On the other hand, to avoid wasteful over-optimization, clock path pessimism should be removed during timing analysis. In order to provide prompt timing information without over-pessimism during iterative optimizations, in this paper, we aim at fast incremental timing and CPPR analysis. We present two delicate techniques, lazy evaluation and lazy propagation, to avoid redundant updates. Our experiments are conducted on the benchmark suite released by TAU 2015 timing analysis contest. Experimental results show that our timer delivers the best results in terms of accuracy, runtime, and memory over all participating teams.

Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis. To avoid exhaustive exploration on all paths in a design, in this paper, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, and dynamic bounding. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.

Traveling ionospheric disturbances (TIDs) induced by acoustic-gravity waves (AGWs) in the neutral atmosphere are observable in trans-ionospheric radio signals such as Global Navigation Satellite System (GNSS) signals. In this research, we designed a wavelet-based method to enhance the detection and estimation for sounding the presence of atmosphere-wave-induced TIDs using measurements collected from GNSS networks near the epicenter of the March 11, 2011 Tohoku-Oki earthquake and the resulting tsunami. A comparison of GNSS/GPS based observations, global ionosphere-thermosphere model (GITM simulations, JPL's tsunami model simulations and ground motions are analyzed to understand the atmosphere-ionosphere responses in this tsunami/earthquake event. Through use of the wavelet coherence analysis, we are able to identify major wave trains presented in the data collected from networks (such as Japan GEONET and U.S. PBO), with different dominant frequency bands and characteristics. They are mostly due to the infrasound signals and gravity waves originated from the epicenter, Rayleigh waves from the ground surface motions, and tsunami propagation.

Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short-path padding (hold time fixing) problem in resilient circuits is far severer than conventional IC design. Therefore, in this paper, we focus on the short-path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we utilize spare cells and a dummy metal to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error-resilient circuits.

Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short path padding (hold time fixing) problem in resilient circuits is severer than conventional IC design. Therefore, in this paper, we focus on the short path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we propose coarse-grained and fine-grained padding allocation methods to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error resilient circuits.

Flip-flops are the most common form of sequencing elements; however, they have a significantly higher sequencing overhead than latches in terms of delay, power, and area. Hence, pulsed-latches are promising to reduce power for high performance circuits. In this paper, we propose a novel pulsed-latch replacement approach to save power and satisfy timing constraints. We fully utilize the intrinsic time borrowing property of pulsed-latches and develop a spiral clustering method with clock gating consideration. In addition, spiral clustering works well for both rectangular and rectilinear shaped layouts; the latter are popular in modern IC design. Experimental results show that our approach can generate very power efficient results.

Clock power is the major contributor to dynamic power for modern integrated circuit design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering several such cells and forming a multibit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, and can even save the clock network power and facilitate the skew control. Hence, in this paper, we focus on postplacement multibit flip-flop clustering to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-sized sequences as our representation. Without enumerating all possible combinations, we identify only partial sequences that are necessary to cluster flip-flops, thus leading to an efficient clustering scheme. Moreover, our fast coordinate transformation also makes the execution of our algorithm very efficient. The experiments are conducted on industrial circuits. Our results show that concise representation delivers superior efficiency and effectiveness. Even under timing and placement density constraints, clock power saving via multibit flip-flop clustering can still be substantial at postplacement.

Traveling ionospheric disturbances (TIDs) induced by acoustic-gravity waves(AGWs) in the neutral atmosphere are subsequently observable in trans-ionospheric Global Navigation Satellite System (GNSS) measurements. Disruptive events on the Earth's surface, such as earthquakes, tsunamis and large explosions are one source of these disturbances. In this study, we apply a wavelet method to enhance the cross-correlation technique for detecting the presence of TIDs in dual frequency IEC time series collected from GNSS networks. Data were collected after the March 11, 2011 earthquake in Japan and the February 27, 2010 earthquake in Chile. Both earthquakes produced large tsunamis. Through use of the wavelet coherence analysis, we are able to find major a wave train, present in the data collected from these networks, with two dominant frequency bands.

Clock power is the major contributor to dynamic power for modern IC design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering such cells and forming a multi-bit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, even can save the clock network power and facilitate the skew control. Hence, in this paper, we focus on multi-bit flip-flop clustering at post-placement to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-size sequences as our representation. Without enumerating all compatible combinations, we extract only partial sequences that are necessary to cluster flip-flops at a time, thus leading to an efficient clustering scheme. Moreover, our coordinate transformation brings fast operations to execute our algorithm. Experimental results show the superior efficiency and effectiveness of our algorithm.

Acoustic-Gravity Waves (AGWs) in the neutral atmosphere can induce disturbances in the ionosphere that are subsequently observable in trans-ionospheric Global Navigation Satellite System (GNSS) measurements. Disruptive events on the Earths surface, such as earthquakes, tsunamis and large explosions are one source of these disturbances. In this presentation, we applied wavelet decomposition to detect the presence of ionospheric disturbances in dual frequency GNSS time series collected from the GEONET (Japan) and SCIGN (Southern California) networks during the Peru tsunami on June 23 2001 and the Chile Tsunami on February 27 2010. Through use of the wavelet decomposition, we are able to find two wave trains, present in the data collected from both networks, with frequencies of approximately 0.0005-0.0011 Hz and 0.0016-0.0167 Hz. The speed and direction of arrival of the disturbances are found through cross-correlating every pair of stations in several sub-areas of each network. These were found to be compatible with the arrival direction and speed of a disturbance created from the Tsunami, with propagation speeds of 101-265 m/s and 559-1195 m/s, respectively.