Synchronizing sequences have been proposed in the late 1960s to solve testing problems on systems modeled by finite-state machines. Such sequences lead a system, seen as a black box, from an unknown current state to a known final one. This paper presents a first investigation of the computation of synchronizing sequences for systems modeled by synchronized Petri nets. In the first part of the paper, existing techniques for automata are adapted to this new setting. Later on, new approaches, that exploit the net structure to efficiently compute synchronizing sequences without an exhaustive enumeration of the state space, are presented.

In this paper, we present an improvement to evaluate the HLA lookahead for distributed DEVS/G-DEVS models in a HLA-compliant environment. The models considered in this distributed simulation have state lifetimes functions of several state variables. We use the graph theory Dijkstra search to compute the different values of the state variables and a mathematical function analysis to determine the lookahead for the model states. We illustrate on an example how this solution extends the range of DEVS/G-DEVS models that can be involved into distributed simulations.

Given a process whose output is a dynamic function of time, the traditional discrete event specification (DEVS) approximates the input, output, and state trajectories through piecewise constant segments, where the segments correspond to discrete time intervals that are not necessarily equal in length. For processes that defy accurate modeling through piecewise constant segments, this paper presents GDEVS, a generalized discrete event specification, wherein the trajectories are organized through piecewise polynomial segments. The utilization of arbitrary polynomial functions for segments promises higher accuracies in modeling continuous processes as discrete event abstractions. In general, discrete event systems including DEVS and GDEVS execute faster on host computers because executions occur corresponding to significant changes in the system unlike in continuous simulations where execution is on a continuous basis. GDEVS' superiority over DEVS lies in its ability to discretize a system characteristic. A key contribution of GDEVS is that it permits the development of a uniform simulation environment for hybrid, i.e. both continuous and discrete, systems. GDEVS is illustrated for a first order system and a hybrid system, with piecewise linear segments. Two representative systems have been modeled under GDEVS and executed on a simulator developed for GDEVS.

In this paper, we focus on an improvement of test pattern generation for circuit descriptions written in hardware description languages according to their behavior. The improvement method stems from the "headlines" defined at the gate level by structural test approaches. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach.>

This paper presents an approach aiming at a significant acceleration of a Behavioral Test Pattern Generation process. Recently, new BTPG methods have been developed, based upon the application of a backtracking search procedure. The approach presented herein reduces the number of backtracks by firstly comparing search strategies and then by defining an improvement criteria.

the object of the system presented in this article is to allow experienced designers to describe their knowledge in the way to chain a group of CAD software to resolve a given problem and this, in the form of production rules. This system establish a clear separation between the competencies of the computer scientist, the experienced designer and the final user. It permits the procedure bank of be CAD system to the considered as a group of basic elements from which chaining scenario adapted to the different design problems can be described so as to guide the final user.

In the development of new CAD tools to be used in processing VLSI type circuits, the need for comprehensive models of electronic systems has become clear. This paper describes a model representation system in which a model, representing multiple views of a real system, at different levels of abstraction, can be constructed. Relationships that exist between different model types and levels of abstraction can be explicitly defined. Applications can, therefore, be decomposed into separate, well defined phases, each phase working with a model suited to it's task.

In this paper, the authors describe methods for generalized deductive fault simulation of digital networks. By introducing the notion of unknown fault list, the propagation algorithm through gates modelized with rise and fall times are simplified with the same accuracy.

The authors propose a three valued model for temporal simulation of logic system. This model is well suited for analysis of hazards and high frequency rejection phenomenas.