The Multi-Layer Satellite Remote Sensing (SRS) integrates data collection by Low Earth Orbit (LEO) satellites and data processing assistance from Medium Earth Orbit (MEO) satellites, thereby playing a crucial role in scientific exploration. However, effectively controlling access to LEO satellites for processing data, especially considering the frequent handovers caused by speed differences, presents a significant challenge to achieving high energy efficiency services. To address this challenge, we explore cooperative dynamic access control based on efficient communication mechanisms, with the aim of prioritizing processed data volume and meeting energy consumption requirements for satellites. Specifically, we formulate the access control issue as an optimization problem and integrate it into the framework of partially observable Markov decision process (POMDP), considering MEO satellites’ limited observation ability. By employing Multi-agent Deep Reinforcement Learning (MADRL), we propose a novel dynamic access control algorithm named DAC to solve our featured problem. Specifically, for improving performance, communication-efficient cooperation among MEOs is enhanced through modeling decision-relevant information of fellow MEO satellites and maximizing mutual information with their actual data to extract precise awareness and enable the generation of concise message. Finally, we conduct comprehensive experiments and an ablation study spanning the Starlink, OneWeb, and Telesat mega-constellations. The results demonstrate that DAC increases the average system data processing volume by at least 13.5%, while meeting energy consumption constraints and outperforming baseline algorithms.

Unmanned aerial vehicles (UAVs) can be flexibly deployed to offload cellular traffic or to provide video services for emergency scenarios without infrastructure. However, the inherent resource allocation and three-dimensional (3D) aerial trajectory design have not been formally studied. In this paper, we study the joint resource allocation and 3D aerial trajectory design for dynamic adaptive streaming over HTTP (DASH)-enabled services in a UAV communication system, where a UAV is employed as a base station for multiuser video streaming. Various factors are taken into account, including video data rate, quality variation, communication outage, play interruption, etc. By adopting a video streaming utility model, two fundamental problems are formulated with different practical aims: the first problem maximizes the minimum utility for all users within a given time horizon such that max-min fairness can be provided, and the second problem minimizes the UAV operation time subject to the individual utility requirement for all users to prolong UAV endurance. To tackle the first non-convex problem, we decouple it into three sub-problems, and a three-stage iterative algorithm is proposed to obtain a suboptimal solution by solving the three sub-problems with successive convex approximation and alternating optimization techniques. An exponential search based algorithm is proposed for the second problem by utilizing the structure of the considered problem and a similar three-stage iterative algorithm. Extensive simulations are carried out to evaluate the performance, and the results show that our proposed designs significantly outperform baseline schemes. Furthermore, our results reveal new insights of UAV movement for video streaming and unveil the tradeoff between utility and quality variance.

Completion time and energy consumption of the unmanned aerial vehicle (UAV) are two important design aspects in UAV-enabled applications. In this article, we consider a UAV-enabled mobile-edge computing (MEC) system for Internet-of-Things (IoT) computation offloading with limited or no common cloud/edge infrastructure. We study the joint design of computation offloading and resource allocation, as well as UAV trajectory for minimization of energy consumption and completion time of the UAV, subject to the IoT devices' task and energy budget constraints. We first consider the UAV energy minimization problem without predetermined completion time, a discretized nonconvex equivalent problem is obtained by using the path discretization technique. An efficient alternating optimization algorithm for the discretized problem is proposed by decoupling it into two subproblems and addressing the two subproblems with successive convex approximation (SCA)-based algorithms iteratively. Subsequently, we focus on the completion time minimization problem, which is nonconvex and challenging to solve. By using the same path discretization approximation model to reformulate problem, a similar alternating optimization algorithm is proposed. Furthermore, we study the Pareto-optimal solution that balances the tradeoff between the UAV energy and completion time. The simulation results are provided to corroborate this article and show that the proposed designs outperform the baseline schemes. Our results unveil the tradeoff between completion time and energy consumption of the UAV for the MEC system, and the proposed solution can provide the performance close to the lower bound.

DC/OS is a widely used distributed operating system that abstracts the resources of light-weighted virtualized datacenters, which is based on Mesos distributed systems kernel and user space services such as Marathon. It automates resource management and process scheduling, thus significantly impacts the performance of datacenters. In this paper, we propose Themis, a flexible, automatic and distributed framework, to evaluate the performance and scalability across both DC/OS and virtualization layer. We can integrate most emerging scale-out datacenter workloads into this framework, and get an easily understandable score that scales with underlying system capacity using a configurable controlled strategy.

Parallelization is an efficient approach to accelerate multi-core, multi-processor and cluster architecture simulators. Nevertheless, frequent synchronization can significantly hinder the performance of a parallel simulator. A common practice in alleviating synchronization cost is to relax synchronization using lengthened synchronous steps. However, as a side effect, simulation accuracy deteriorates considerably. Through analyzing various factors contributing to the causality error in lax synchronization, we observe that a coherent speed across all nodes is critical to achieve high accuracy. To this end, we propose wall-clock based synchronization (WBSP), a novel mechanism that uses wall-clock time to maintain a coherent running speed across the different nodes by periodically synchronizing simulated clocks with the wall clock within each lax step. Our proposed method only results in a modest precision loss while achieving performance close to lax synchronization. We implement WBSP in a many-core parallel simulator and a cluster parallel simulator. Experimental results show that at a scale of 32-host threads, it improves the performance of the many-core simulator by 4.3χ on average with less than a 5.5 percent accuracy loss compared to the conservative mechanism. On the cluster simulator with 64 nodes, our proposed scheme achieves an 8.3χ speedup compared to the conservative mechanism while yielding only a 1.7 percent accuracy loss. Meanwhile, WBSP outperforms the recent proposed adaptive mechanism on simulations that exhibit heavy traffic.

This paper presents PARD, a programmable architecture for resourcing-on-demand that provides a new programming interface to convey an application's high-level information like quality-of-service requirements to the hardware. PARD enables new functionalities like fully hardware-supported virtualization and differentiated services in computers. PARD is inspired by the observation that a computer is inherently a network in which hardware components communicate via packets (e.g., over the NoC or PCIe). We apply principles of software-defined networking to this intra-computer network and address three major challenges. First, to deal with the semantic gap between high-level applications and underlying hardware packets, PARD attaches a high-level semantic tag (e.g., a virtual machine or thread ID) to each memory-access, I/O, or interrupt packet. Second, to make hardware components more manageable, PARD implements programmable control planes that can be integrated into various shared resources (e.g., cache, DRAM, and I/O devices) and can differentially process packets according to tag-based rules. Third, to facilitate programming, PARD abstracts all control planes as a device file tree to provide a uniform programming interface via which users create and apply tag-based rules.

Datacenters consolidate diverse applications to improve utilization. However when multiple applications are co-located on such platforms, contention for shared resources like Networks-on-Chip (NoCs) can degrade the performance of latency-critical online services (high-priority applications). Recently proposed bufferless NoCs have the advantages of requiring less area and power, but they pose challenges in quality-of-service (QoS) support, which usually relies on buffer-based virtual channels (VCs). We propose QBLESS, a QoS-aware bufferless NoC scheme for datacenters. QBLESS consists of two components: a routing mechanism (QBLESS-R) that can substantially reduce flit deflection for high-priority applications, and a congestion-control mechanism (QBLESS-CC) that guarantees performance for high-priority applications and improves overall system throughput. We use trace-driven simulation to model a 64-core system, finding that when compared to BLESS, a previous state-of-the-art bufferless NoC design, QBLESS improves performance of high-priority applications by an average of 33.2%.

Cloud computing has demonstrated tremendous capability in a wide spectrum of online services. Virtualization provides an efficient solution to the utilization of modern multicore processor systems while affording significant flexibility. The growing popularity of virtualized datacenters motivates deeper understanding of the interactions between virtual machine management and the micro-architecture behaviors of the privileged domain. We argue that these behaviors must be factored into the design of processor microarchitecture in virtualized datacenters. In this work, we use performance counters on modern servers to study the micro-architectural execution characteristics of the privileged domain while performing various VM management operations. Our study shows that today's state-of-the-art processor still has room for further optimizations when executing virtualized cloud workloads, particularly in the organization of last level caches and on-chip cache coherence protocol. Specifically, our analysis shows that: shared caches could be partitioned to eliminate interference between the privileged domain and guest domains; the cache coherence protocol could support a high degree of data sharing of the privileged domain; and cache capacity or CPU utilization occupied by the privileged domain could be effectively managed when performing management workflows to achieve high system throughput.

As different workloads require different processor resources for better execution efficiency, recent work has proposed composable chip multiprocessors (CCMPs), which provide the capability to configure different number and types of processing cores at system runtime. However, such composable architecture poses a new significant challenge to system scheduler, that is, how to ensure priority-based performance for each task (i.e. fairness), while exploiting the benefits of composability by dynamically changing the hardware configurations to match the parallelism requirements in running tasks (i.e. resource allocation). Current multicore schedulers fail to address this problem, as they traditionally assume fixed number and types of cores.

With recent advances of processor technology, the LRU based shared last-level cache (LLC) has been widely employed in modern Chip Multi-processors (CMP). However, past research indicates that the cache performance of the LLC and further of the CMP processors may be degraded severely by LRU under the occurrence of the inter-thread interference or the excess of the working set size over the cache size. Existing approaches tackling this performance degradation problem have limited improvement of an overall cache performance because they usually focus on a single type of memory access behavior and thus lack full consideration of tradeoffs among different types of memory access behaviors. In this paper, we propose a unified cache management policy called Partitioning-Aware Eviction and Thread-aware Insertion/Promotion policy (PAE-TIP) that can effectively enhance capacity management, adaptive insertion/promotion, and further improve the overall cache performance. Specifically, PAE-TIP employs an adaptive mechanism to decide the position where to put the incoming lines or to move the hit lines, and chooses a victim line based on the target partitioning given by utility-based cache partitioning (UCP). In our study, we show that PAE-TIP can cover a variety of memory access behaviors simultaneously and provide a good tradeoff for overall cache performance improvement while retaining competitively low hardware and design overhead. The evaluation conducted on 4-way CMPs shows that the PAE-TIP-managed LLC can improve overall performance by19.3% on average over the LRU policy. Furthermore, the performance benefit of PAE-TIP is 1.09x compared to PIPP, 1.11x compared to TADIP and 1.12x compared to UCP.