Flexible electronics (FE) based on indium gallium zinc oxide thin-film transistors (IGZO-TFTs) are emerging for ultra-low-power wearable applications. However, lack of packaging, limited pins, and high device variability make conventional Automatic Test Equipment (ATE) impractical for testing analog/mixed-signal circuits in FE. This work presents a dual-purpose ring oscillator (RO) and voltage-controlled oscillator (VCO) serving as functional timing blocks and core structures for a distributed delay-based BIST framework. The oscillators achieve 1100x area reduction and 5600x lower power than previous IGZO-TFT designs. Lightweight digital BIST embedded within each RO stage enables stage-wise delay monitoring for defect detection. The BIST achieves 93% defect coverage for individual defects and 88% for multiple simultaneous defects, with only 3% power overhead

Memristor-based computation-in-memory (CiM) architectures address the growing computational demands of AI accelerators by enabling analog matrix-vector multiplication (MVM) directly within the memory array. Passive (selectorless) memristive crossbars are particularly attractive for such architectures due to their high density and compatibility with back-end-of-line fabrication. Here, AI model parameters are stored as memristor conductances, and MVM is performed in situ by activating multiple rows simultaneously and sensing the resulting column currents. As a result, column currents become the primary observable, making column-level fault detection more relevant for AI workloads than conventional March-based cell-level tests, which are specially time - and energy-intensive for passive crossbars due to specialized biasing methods. To address this, we propose a current-based testing methodology tailored to passive crossbars that detects and diagnoses faulty columns while accounting for non-idealities such as sneak-path currents, line resistance, and process variations. Faulty columns are detected by programming all cells to a uniform state and measuring column-current deviations, followed by targeted test patterns to estimate per-column fault density. On a $64 \times 64$ array, the proposed approach achieves 100% faulty column detection, 98% overall fault coverage, and a $2.3 \times$ speed-up in test time compared to conventional March tests. Hence, providing a fast and efficient solution for manufacturing screening of passive crossbars with sufficient diagnostic resolution to support systemlevel fault tolerance for AI applications.

Micro-Electro-Mechanical Systems (MEMS) accelerometers play a critical role in safety-oriented applications, necessitating precise calibration methods that adhere to National Institute of Standards and Technology (NIST) guidelines of 2% accuracy. Traditional calibration techniques, relying on physical stimuli during the production phase, are often cost-prohibitive and time-consuming. This paper presents a novel calibration methodology utilizing electrical stimulation, specifically a DC stimulus, to excite the accelerometer. This approach simplifies the calibration electronics compared to AC stimulus calibration methods. By applying six distinct DC steps and measuring the resulting change in capacitance, we establish a correlation between the electrical response and the physical sensitivity of a selected batch of sensors. We employ machine learning algorithms to develop a predictive model that estimates the sensitivity of additional sensors within the batch based solely on the DC stimulus data. Experiments show that the proposed DC stimulus-only calibration method can achieve a root mean square (RMS) error of 1.15% for lot-to-lot process variations and 0.36% for within-lot process variations. This innovative calibration strategy not only enhances accuracy but also significantly reduces both testing costs and time.

Integration of analog and RF circuits with advanced node digital systems has leapfrogged analog circuits by several technology nodes. This has resulted in higher defect rates as well as higher process variations. Another point of pressure is that some application domains, such as the automotive industry, require very low defect rates. To ensure that the circuits are thoroughly tested without increasing the test cost severely, test optimization methods can be applied. Examples of test optimization can include the use of alternate tests, reduced test sets, and built-in self-tests. Defect coverage of the optimized tests needs to be evaluated to ensure high-quality products. For analog circuits, defect definitions are generally continuous and minimum detectable deviation (of hard and soft defects) may differ from one test to another. Finding this detectability point is important to compare potential test conditions. In this paper, we propose an algorithm to determine the minimum detectable defect severity for each defect under given test conditions. Ultimately, this information can be used to find the most sensitive test method that already covers the detection limit of other methods. Experiments on an 8-bit ADC circuit show that the proposed algorithm finds the defect detectability limits of different test methods in only a few search steps and yields accurate results.

Matched circuit components are crucial for maximum efficiency in radio frequency (RF) systems, necessitating accurate load impedance monitoring. This paper proposes a method using reference point optimization with periodic structures for precise, low-overhead impedance measurements suitable for Built-in Self-Test (BIST). The novel technique uses a linear matching network and voltage detectors to sense load variations. A periodic structure measures voltages, and a multi-step algorithm selects optimal reference points to determine the load impedance.

The objective of fault simulation is to estimate the fault coverage of a given test input. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. The goal of this paper is to bridge the gap between available transistor-level fault simulation tools, where fault simulation can be accurate, and behavioral abstraction levels, where simulation time can be shorter. We aim to achieve this by judiciously adding various functional enhancements to individual functional blocks from a list of templates into their behavioral model until the responses at the two abstraction levels match. Transistor-level simulations are only limited to smaller functional blocks, where they are feasible, and individual fault responses are captured for behavioral simulations. Experimental results on two example circuits, a flash ADC and a PLL, show that accurate simulations can be achieved at a fraction of the simulation time.

Micro Electro-Mechanical Systems (MEMS) accelerometers are utilized in safety-critical applications, including airbags, aircraft, medical devices, as well as various consumer electronic applications. Despite providing highly accurate results, they require calibration during production and periodic recalibration due to potential degradation over time. The National Institutes of Standards and Technology (NIST) stipulates that the accuracy of motion sensors used in safety-critical applications must be maintained within a 1% error margin. In our research, we propose an electrical stimulus-based calibration method for sensors during production and in-field use. In-field electrical stimulation and calibration can facilitate prolonged sensor operation without the need to remove the sensor from its environment. Although electrical stimulation has been suggested as a replacement for physical stimulation to reduce testing costs for sensors, it has not yet demonstrated the ability to meet the 1% error requirement mandated by NIST safety standards. We propose an incremental sensor-based model that can correlate sensor sensitivity degradation and process variation to its electrical response for in-field monitoring. Simulations demonstrate that the model can forecast sensitivity changes within a 1% error margin. Additionally, we have developed a cost-effective rotating test platform for calibrating and measuring accelerometer sensitivity. This method utilizes wireless technology to transmit accelerometer data to a computer, eliminating the necessity for lengthy cables. The rotating platform can produce various accelerations at different distances along the radius by spinning at different RPMs, leveraging centripetal force to apply a fixed acceleration at a set RPM.

Recently, many applications have been developed using mm-Wave devices with different specifications and requirements. The semiconductor manufacturing technology has improved the bandwidth and power delivery of integrated circuits. For mm-wave devices, on-board or on-chip antennas are often the performance limiting factors. With wide-ranging specifications, automation of antenna designs has become necessary to find the optimal sizing and materials. Typically, design optimization relies on being able to conduct many simulations to evaluate the performance of design instances. However, electromagnetic (EM) simulations are very time-consuming. Surrogate model-based techniques have been developed to minimize the number of simulations. For large sets of design parameters and large input space, relying on a single model may not provide the best solution. In this paper, we propose an evolutionary search-based algorithm for the multi-objective antenna design optimization problem using multiple surrogate models to determine candidates for EM simulations. The proposed method models the reflection coefficient as a function of frequency and antenna gain as a function of angle and tries to concurrently maximize bandwidth and field of view. Two architectures have been designed for evaluation with 5 and 14 design parameters. The proposed technique can provide a large bandwidth and field of view with only several hundred samples.

This paper introduces a sensor calibration and gas source localization method designed for the challenging task of detecting gas leaks in open environments using multiple low-cost sensors that can be randomly distributed in a coverage area. Low-cost sensors, such as Metal Oxide resistive sensors, suffer from very large sensor-to-sensor variations in their detection range, noise floor, and limited sensitivity. The proposed approach begins with a self-calibration process that leverages known source locations to fine-tune their performance parameters. The independent calibration of sensors results in more precise measurements. Furthermore, we propose a computationally efficient technique that achieves high-precision gas source localization. Our methodology is compared with existing localization techniques to demonstrate its effectiveness.

Integrating analog circuits with the most advanced digitally-tuned processes increases the defect rates and the risk of in-field wear out. Coupled with the reduced accessibility arising from this level of integration, increasing defect rates necessitate systematic approaches to analog testing. Structural built-in self-test (BIST) for analog circuits can reduce test development complexity. In this paper, we propose a robust and low-cost structural BIST method for analog circuits. The proposed method relies on perturbing the analog circuit at an injection point and observing the result at an observation point as a digitally measurable time delay. Injection can be achieved via simple ON/OFF keying while the observation can be achieved by a self-referencing comparator. Multiple injection points can be selected at low cost (single transistor) while the observation circuit can be shared across many injection points and across different circuit blocks. The proposed method is demonstrated on two circuits, showing that 96% of catastrophic faults can be detected with the proposed approach with six injection points.

RF systems, including RF MIMO RADARs, are increasingly integrated with digital systems in fine-geometry processes. Due to the prevalent use of RF MIMO RADARs in automotive and other safety-critical applications, in-field testing and tuning of these systems are needed to meet performance and safety targets. The fundamental performance targets of an RF MIMO system include the signal-to-noise ratio at the end of the receiver chain, matching characteristics between different signal paths, gain, noise figure, and linearity of the RF front end. In a RADAR device, matching between signal paths affects the angular resolution of the system. The gain and noise figure of the receiver control the maximum distance and the smallest object that the system can detect. In this work, we present a global tuning algorithm for RF MIMO RADARs to meet critical system performance targets while minimizing power consumption. The efficacy of the method is demonstrated with extensive simulations and hardware experiments.

Hardware imperfections and environmental factors create mismatches between transmit and receive paths. In MIMO mm-Wave radars, determining and eliminating gain and phase mismatches are required to increase the overall accuracy of range and angle of arrival (AoA) estimation. Measurement of mismatches, particularly phase mismatch, requires complex test setups and external equipment, such as a network analyzer. This paper proposes an on-chip (or on-board) measurement method for mm-Wave radars to determine the mismatches using RF power detectors. The proposed method relies on mutual coupling between transmitter and receiver antennas. A detailed mathematical analysis of the proposed method along with boundary conditions is presented. Simulations and hardware measurements using a cascaded mm-Wave radar device shows that the proposed phase mismatch extraction technique provides very accurate results within defined boundary conditions.

Millimeter-wave radars are used to estimate the position of an object relative to the radar position in terms of the range, R, azimuth angle, θ, and elevation angle, ϕ. Typical radar operation includes transmitting a chirp signal, receiving the signal reflected by the objects in the environment, and mixing these signals at the receiver chain. For multiple antenna systems, the range can be calculated for each transmit and receive antenna, yielding multiple measurements. To increase the accuracy, these results are averaged. Angle estimation makes use of the phase differences between different antenna paths. Since there is only one calculation across all antenna elements, this calculation does not benefit from averaging. In addition to these random errors, systemic errors occur in the process of angle calculation. In this paper, we analyze the root cause of the systemic error and propose solutions to correct for this error to increase angle estimation accuracy.

The detail routing process is by far the most time consuming during the physical design flow. Routing starts with an estimation of timing slacks and aims to meet the timing specifications at signoff. In this paper, we propose an improved method to predict the net delays using RandomForestRegressor and thereby predict critical paths early on at the placement stage. Quick timing prediction is also essential in making time-sensitive edits to stepping of the chip based on post-Si feedback. The proposed algorithm is based on five novel features, namely, targeted feature selection, introduction of a one-hot encoding scheme, an outlier identification method, post-route buffer-bloat prediction, and post-route cell sizing prediction. Experimental results on academic benchmarks and industry circuits, both on advanced 10nm process node show that the proposed algorithm has led to significant improvements in accurately predicting timing slacks when compared with state of the art. The proposed algorithm predicts slack within 0.598% of signoff results, whereas the state of art results are erroneous by an average of 53.33% for the same metric. Overall time savings of 44.1% is seen when compared to running the traditional flow, and savings of 90% is seen for obtaining the timing results.

Involvement of many parties in the production of integrated circuits (ICs) makes the process more vulnerable to tampering. Consequently, IC security has become an important challenge to tackle. One of the threat models in hardware security domain is the insertion of unwanted and malicious hardware components, known as Hardware Trojans (HTs). A malicious attacker can insert a small modification into the functional circuit that can cause havoc in the field. To make the Trojan circuit stealthy, trigger circuits are typically used. The purpose of the trigger circuit is to hide the Trojan activity during post-production testing, and to randomize activation conditions, thereby making it very difficult to diagnose even after failures. Trigger mechanisms for Trojans typically delay and randomize the outcome based on a subset of internal digital signals. While there are many different ways of implementing the trigger mechanisms, charge based mechanisms have gained popularity due to their small size. In this paper, we propose a scheme to ensure that the trigger mechanisms are activated during production testing even if the conditions specified by the malicious attacker are not met. By disabling the mechanism that makes the Trojan stealthy, any of the parametric techniques can be used to detect Trojans at production time. The proposed technique relies on supply pulsing, where an increased potential difference between the gate and bulk of the active transistor in the output stage generates an alternate charge path for an otherwise unreachable capacitor and bypasses the input conditions to the trigger mechanism. SPICE simulations show that our method works well even for the smallest Trojan trigger mechanisms.

In this work, we present a method for detecting anomalous chemical sensors using contrastive learning-based framework. In many practical systems, an array of multiple chemical sensors are used. Some of the sensors may malfunction due to sensor drift and chemical poisoning. In standard contrastive learning, the aim is to learn representations that will have maximum agreement among data samples of the same concept while having a minimal agreement with data samples from other concepts. In this work, we adapt standard contrastive learning to learning useful representations for out-of-distribution sample detection. Furthermore, we compare the proposed framework with the cosine similarity measure and a novel similarity measure based on the ℓ1norm. Our experimental results show that our approach achieves higher AUC scores (93.6%) than baseline methods (90.1%).

Due to increasing performance demands, RF circuits are increasingly integrated into fine-geometry processes which necessitates their post-production and in-field calibration. One of the most important parameters for RF performance is matching between various nodes in the circuit. Process, voltage, and temperature (PVT) variations and other environmental conditions such as objects in the near-field of an antenna can cause shifts in the RF matching between sources and the loads. To compensate for such shifts, generally a tunable element or a network is incorporated between the source and the load, which will enable post-production calibration. In this paper, we present a tuning algorithm that adjusts the tuning structures until a match is detected via built-in measurements. The proposed technique can be used both for post-production and for in-field calibration. It only requires three strategically placed power detectors along the transmission line connecting the source to the load and simple computations. Experimental results based on simulations and hardware measurements show that the technique can provide highly accurate matching between a source and a load component.

The need for digital calibration due to large variations in fine-geometry processes as well as the need for performance locking mechanisms to prevent IC piracy have resulted in the prevalent use of digital assistance for analog circuits. The same issues also make analog circuits vulnerable to infield performance degradation either due to wearout or due to potential attacks by adversaries. Unfortunately, most of the vulnerabilities are activated after the device is deployed. In order to ensure secure and reliable operation of the system, abrupt performance fluctuations in analog circuits need to be detected in the field. The detection method needs to be robust with respect to process variations, low-cost, and avoid providing information that attackers can use to compromise the circuit. In this paper, we propose a simple method for detecting performance degradation of digitally-assisted analog circuits using simple circuit elements, such as level shifters and inverters. The proposed method identifies an easy-to-monitor invariant in the circuit that is correlated to performance variables but this correlation is not known to attackers. The proposed method is demonstrated on a low drop out voltage regulator (LDO). Experimental results confirm that the proposed method can detect deviations in performance due to the alteration of calibration or performance locking bits.

A range of medical issues are treated by simple biomechanical implants to regulate fluid pressure and flow (e.g. valves, shunts). With moving parts in fluid, these implants are vulnerable to biological failures (infection, migration), mechanical failures (clogging, cracking), and parametric failures (change in flow resistance, cracking pressure). Existing biomechanical implants only show failure by clinical symptoms, which may be catastrophic. A means to better observe device behavior and predict failure is necessary. We explore merging biomechanical implants with low-footprint passive electronics, creating bio-electro-mechanical (BEM) devices and thereby allowing external monitoring. Passive feedback signals (RF backscatter) may be interpreted by a model to extract flow parameters and predict failure. A model may be trained by benchtop testing, to correlate direct measurements (flow, pressure) with passive device signals. Benchtop failure simulation (accelerated aging, simulated biofouling) may better train the model for failure prediction. This paper uses long-term pressure/flow testing data from a simple biomechanical device (hydrogel valve for hydrocephalus) as a test case for extracting predictive signals of imminent device failure.

With increasing pressure to obtain near-zero defect rates, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, power converters, and data converters. This article presents an extremely low-cost built-in self-test technique for LDOs, specifically designed for fault detection. The methodology relies on exciting the LDO loop at the voltage reference input via a pseudo-random signal with white noise characteristics and observing the response from the output of LDO via all-digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with an LDO as a device under test is designed in 65nm technology. Fault simulations performed at the transistor level show that all resistive open/short defects in circuit components can be detected even if they do not cause a catastrophic failure in the LDO response. The proposed technique is validated with hardware using off-the-shelf components.

As the Internet of Things (IoT) is growing rapidly, there is an emerging need to facilitate development of IoT devices in the design cycle while optimized performance is obtained in the field of operation. This article develops reconfiguration approaches that enable post-production adaptation of circuit performance to enable RF IC reuse across different IoT applications. An adaptable low noise amplifier (LNA) is designed and fabricated in 130-nm CMOS technology to investigate the post-production reconfiguration concept. A statistical model that relates circuit-level reconfiguration parameters to circuit performances is generated by characterizing a limited number of samples. A deep learning algorithm is used to generate the model. This model is used to predict the performance parameters of the device in the field. The estimation error for LNA performance parameters are obtained in the simulation environment as well as chip measurements.

Sensor drift is a major problem in chemical sensors that requires addressing for reliable and accurate detection of chemical analytes. In this paper, we develop a causal convolutional neural network (CNN) with a Discrete Cosine Transform (DCT) layer to estimate the drift signal. In the DCT module, we apply soft-thresholding nonlinearity in the transform domain to denoise the data and obtain a sparse representation of the drift signal. The soft-threshold values are learned during training. Our results show that DCT layer-based CNNs are able to produce a slowly varying baseline drift signal. We train the CNN on synthetic data and test it on real chemical sensor data. Our results show that we can have an accurate and smooth drift estimate even when the observed sensor signal is very noisy.

Due to their simplicity, low power consumption, and high-performance, direct conversion transceivers are used widely in RF-front ends. Direct conversion receivers demodulate the signal to its in-phase (I) and quadrature (Q) parts by multiplying the RF signal with two signals with a 90°phase separation. To achieve best performance, I and Q paths should be matched in terms of gain, phase, and have no DC offset. Any impairment in these parameters would result in reduced performance and higher bit error rate. In this work, we propose a BIST scheme for IQ mismatch compensation with low overhead for direct conversion receivers. We use an envelope detector to detect the combined amplitude of the I and Q signals and we use this information to iteratively correct for the receiver’s IQ imbalance. The only requirement on the power detector is a small linear dynamic range (15dB). The conversion gain of the power detector does not need to be known. The proposed method can be used in the mission mode in the background to calibrate any deviations in performance. After the receiver’s IQ imbalance is corrected, it can be used to measure and compensate for any transmitter IQ imbalance in a loopback mode. Simulations and hardware measurements confirm that the proposed technique can measure the imbalances with high accuracy.

Micro Electro-Mechanical Systems (MEMS) accelerometers are used in safety critical applications, such as airbags and airplanes. While providing very accurate results, they can degrade over time due to many wearout mechanisms. According to the National Institutes of Standards and Technology (NIST), the accuracy of motion sensors used in safety critical applications needs to be maintained within 1% error. In-field electrical stimulation and calibration can enable long-term sensor operation without removing the sensor from its environment. While electrical stimulation has been proposed to replace the physical stimulation to reduce testing cost for sensors, it has not yet been shown to achieve the 1% error requirement as required by the NIST standard of safety. In this paper, we propose an incremental sensor-based model that can relate the degradation in the sensitivity of the sensor to its electrical response for infield monitoring. In order to extract such a relation, we need to generate multiple sensitivity states for the sensor however, which is not possible using the normal mode of operation. We propose to temporary place the sensor in an enhanced state where the sensitivity can be changed also via electrical signalling, thereby generating an adequate number of measurements to solve for model coefficients. We show through simulations and hardware experiments that the model can predict the sensitivity changes within 1% error.

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

With the increasing complexity of electronic components in critical applications, pressure on single components to have zero defects is also increasing. Thus there is a need to explore built-in self-test and other non-traditional test techniques for mixed-signal circuits, such as data converters, phase locked loops and power converters. In this paper, we present an extremely low cost, digital built-in self-test methodology for Low Dropout Regulators (LDO), specifically used for defect detection. The technique relies on perturbing the LDO loop at the reference voltage input via pseudo random binary sequence which has white noise characteristics and cross correlating the output of LDO with input excitation using only digital circuits, thus inducing low power and area overhead. The built-in self-test technique together with an LDO is designed using 65nm TMSC technology. Transistor level structural fault simulations display that all inserted faults can be detected even if they do not change the DC level of the LDO output.

Large, open, public events, such as marathons and festivals, have always presented a unique safety challenge. These sprawling events, which can take up entire city blocks or stretch for many miles, can draw tens to hundreds of thousands of spectators and in some cases have open admission. As it is impracticable to guarantee the subjection of every event-goer to a security screening, we propose a crowd-based explosive detection system that uses a multitude of low-cost ChemFET sensors which are distributed to attendees. As the sensors offer limited accuracy, we further propose a server-based decision-making framework that utilizes a two-level feedback loop between the sensors and the server and explores spatial and temporal locality of the collected data to overcome the inherent low-accuracy of individual sensors. We thoroughly explore two distinct detection schemes, stressing their performance under a myriad of conditions, thus showing that such a crowd-based detection system comprised of low-cost and low-accuracy sensors can deliver high detection accuracy with minimal false positives.

RF sensor technology in mm-wave range has improved significantly in recent years, which led to its widespread use in mission-critical systems, such as automotive radar. With the advent of multi-antenna systems, cascaded radar designs has gained prominence to increase resolution in terms of distance, speed, and angle. However, the performance of the radar systems can be highly dependent on dynamic conditions and they may require in-field calibration, specifically in terms of magnitude and phase mismatches of gain and input reflection coefficient. While in-field measurement of gain using built-in power sensors is more or less straightforward, measurement of the reflection coefficient requires the implementation of an N-port reflectometer on the chip. In this paper, we present an analytical model for noise and gain imperfections in N-port network analyzers. Based on this model, we propose a methodology for optimizing the design of the N-port reflectometer to obtain the highest accuracy under given realistic constraints, such as coupler gain/loss, splitter loss, power detector non-idealities, and noise.

This article focuses on designing an energy-efficient image recognition system for marine monitoring. One of the main challenges of an underwater imaging system is the strict power consumption constraints due to the limited on-site resources. Considering the need for continuous operation in different water turbidity levels and background illumination conditions, an energy-efficient approach is needed for the effective utilization of the resources. In this work, we propose a recognition framework that will adaptively adjust the system parameters, such as camera frame rate and LED illumination level, based on the environmental conditions to optimize the energy consumption while ensuring a high recognition accuracy. The first part of the proposed decision system contains the convolutional neural network (CNN)-based animal recognition block which is used for obtaining the confidence level for a single frame. The second part is the adaptive decision block that dynamically changes the system parameters and combines the results of the recognition block for multiple frames based on the environmental conditions. In our experiments, we have used nearly 8000 underwater images for training and testing the single frame recognition block and used nearly 200 different video sequences for training and testing the adaptive decision block. Based on measurements of a hardware framework composed of a Raspberry Pi 3 Model B, a Pi NoIR Camera v2.1, and 850 nm LEDs, the proposed system achieves up to 92.7% energy savings with a comparable recognition performance by dynamically changing the frame rate and emitted light intensity based on water turbidity and background illumination level.

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

While Volatile Organic Compounds (VOC) and ammonia have a place in our daily lives, their leakage into the environment is harmful to human health. In order to prevent and detect gaseous leaks of harmful VOCs, a cyber-physical system (CPS) comprised of ordinary people or first responders is proposed. This CPS uses small, low-cost sensors coupled to smart phones or mobile devices with the necessary computation and communication capabilities. The efficacy of such a CPS hinges on its ability to address technical challenges stemming from the fact that identically produced sensors may produce different results under the same conditions due to sensor drift, noise, or resolution errors. The proposed system makes use of time-varying signals produced by sensors to detect gas leaks. Sensors sample the gas vapor level in a continuous manner and time-varying sensor data is processed using deep neural networks. One of the neural networks (NN) is an energy efficient Additive Neural Network (AddNet) which can be implemented in host devices. The second NN is the discriminator of a GAN and the third a regular convolutional NN. AddNet produces comparable VOC gas leak detection results to regular convolutional networks while reducing area requirements by two thirds.

Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations in the field can lead to significant testing and validation challenges. For example, designers must ensure that FHE devices continue to meet their specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. We develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation. We validate the proposed approach using an FHE prototype and COMSOL Multiphysics simulations.

Ensuring security of electronic hardware has recently attracted much attention. While a majority of the work in this domain has focused on integrated circuits, printed circuit boards are just as susceptible to unwanted and unauthorized modifications during their manufacturing. Prior work in this domain has shown some examples of failures that can stem from intentional and unintentional board-level modifications. In this paper, we provide an in-depth analysis of previously unexplored board-level modifications and show that a number of attack modes cannot be detected using traditional methods. We also show that it is possible to detect attack modes that are most damaging to the board operation by redesigning the board with additional accessibility and adding specialized test sequences.

We propose a fully differential, synthesizable zoom-ADC architecture with a passive loop filter for low-frequency Built-In Self-Test (BIST) applications, along with a synthesis tool that can target various design specifications. We present the detailed ADC architecture and a step-by-step process for designing the zoom-ADC. The design flow does not rely on the extensive knowledge of an experienced ADC designer. Two ADCs have been synthesized with different performance requirements in the 65nm CMOS process. The first ADC achieves a 90.4dB Signal-to-Noise Ratio (SNR) in 512μs measurement time and consumes 17μW power. The second design achieves a 78.2dB SNR in 31.25μs measurement time and consumes 63μW power.

As process variations increase and devices get more diverse in their behavior, using the same test list for all devices is increasingly inefficient. Methodologies that adapt the test sequence with respect to lot, wafer, or even a device's own behavior help contain the test cost while maintaining test quality. In adaptive test selection approaches, the initial test list, a set of tests that are applied to all devices to learn information, plays a crucial role in the quality outcome. Most adaptive test approaches select this initial list based on fail probability of each test individually. Such a selection approach does not take into account the correlations that exist among various measurements and potentially will lead to the selection of correlated tests. In this work, we propose a new adaptive test algorithm that includes a mathematical model for initial test ordering that takes correlations among measurements into account. The proposed method can be integrated within an existing test flow running in the background to improve not only the test quality but also the test time. Experimental results using four distinct industry circuits and large amounts of measurement data show that the proposed technique outperforms prior approaches considerably.

Globalized supply chain for electronic circuit manufacturing has reduced the production cost considerably. However, it also presents a challenge since many companies/players contribute to the product and it is not always possible to control or monitor every third-party employee or contractor that takes part in the process. A design house that relies on a foundry for manufacturing needs to ensure that the manufactured devices conform to the agreed-upon process model between the design house and the foundry. Potential deviation from the process model may be due to incidental quality control issues, or due to malicious modifications to the process or circuit layout with the intent of doing harm during in-field operation. In this paper, we present a multivariate methodology to detect even small process and layout level modifications to the circuit by using mission-mode specifications as well as enhanced test modes. We present an algorithm for detecting process/layout modifications and for selection of test inputs to be used in the detection process. Experimental results on an LNA circuit show that the proposed technique can achieve high authentication accuracy even for a single device with a negligible false positive rate.

Per-device adaptive test is a promising direction with the best trade-off between test quality and test time so far. In this work, we propose a method for online assessment of the information content of the next test in the test queue. This assessment can be used to tune the trade-off between test quality and test time of a per-device adaptive test. Since majority of specification parameters are correlated, the overall information content of multiple tests is difficult to extract. We model multi-variate correlations among specification parameters and take these correlations into account to estimate the multivariate overall information utility of a given set of tests. The proposed method can be integrated within an existing adaptive test flow (per-device or per-wafer) that runs in the background. Experimental results using 3 distinct industry circuits and sizable data show that the proposed technique can finely tune the trade-off, even achieve zero test escape rates with appreciable test time savings.

Internet of Things (IoT) nodes used in environmental monitoring and smart city applications are becoming increasingly prevalent with over $200B projected market potential. These nodes typically employ one-way communications using a high-end transmitter without a corresponding receiver. Testing of such transmitter-only systems poses an additional challenge. Due to the lack of a receiver, low-cost test techniques, such as loop-back, cannot be used. In this paper, we present a low overhead built-in self-test (BIST) technique to characterize imbalances of IQ transmitters without a receiver, both for post-production and in-field test purposes. The proposed BIST uses simple circuitry and a single test setup. The target parameters are analytically computed independent from internal BIST parameters which eliminates the need for initial calibration phase. All measurements are in DC and no external RF signal generation is required. The overall measurement time, including the computation time, is less than 2ms. Simulation and measurement results show that the proposed method provides adequate estimation accuracy for digital calibration.

This special session will focus on new ways of performing calibration and test of on chip circuits that historically were performed on ATE. The presentation in this special session will demonstrate how these new test and calibration techniques help to reduce cost and increase the quality of semiconductor shipped into the field.

With increasing diversity of supply chains from design to delivery, there is an increasing risk that unauthorized changes can be made within an IC. One of the motivations for this type of change is to learn important information (such as encryption keys, spreading codes) from the hardware, and transmit this information to a malicious party. To evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this article, we present several signal processing techniques to detect unauthorized transmissions which can be hidden within the legitimate signal. We employ a scheme where the legitimate transmission is configured to emit a single sinusoidal waveform. We use time and spectral domain analysis techniques to explore the transmit spectrum. Since every transmission, no matter how low the signal power is, must have a spectral signature, we identify unauthorized transmission by eliminating the desired signal from the spectrum after capture. Experiment results show that when spread spectrum techniques are used, the presence of an unauthorized signal can be determined without the need for decoding the malicious signal. The proposed detection techniques need to be used as enhancements to the regular testing and verification procedures if hardware security is a concern.

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. Since trojans may be triggered in the field at an unknown instance, it is important to detect their presence at runtime. However, it is difficult to run sophisticated detection algorithms on these devices due to limited computational power and energy and, in some cases, lack of accessibility. This article presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enters the test mode , a predefined test application is run on the device repetitively for a known period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operating bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicate the presence of unknown (unauthorized) activity. Hence, we are able to differentiate trojan activity without using a golden reference , or any knowledge of the attributes of the trojan activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120cm distance.

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High-frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency and smaller form factor. Unfortunately, they are also subject to higher process variations, and faster in-field degradation, jeopardizing stable operation of the power supply. This article presents a technique to track changes in the dynamic loop characteristics of DC-DC converters without disturbing the normal mode of operation using a white noise–based excitation and correlation. Using multiple points for injection and analysis, we show that the degraded part can be diagnosed to take remedial action. White noise excitation is generated via a pseudo-random disturbance at reference, load current, and pulse-width modulation (PWM) nodes of the converter with the test signal energy being spread over a wide bandwidth, without significantly affecting the converter noise and ripple floor. The impulse response is extracted by correlating the random input sequence with the disturbed output generated. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the-shelf power converter, LM27402, is used as the device-under-test (DUT) for experimental verification. Experimental results show that the proposed technique can estimate converter natural frequency and quality factor ( Q -factor) within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance. For the diagnosis purpose, a measure of inductor's DC resistance (DCR) value, which is the inductor's series resistance and indicative of the degradation in inductor's Q -factor, is estimated within less than ±1.6% error margin.

Future RF transceivers are expected to integrate the entire system, from baseband to antenna. Many emerging applications use beam forming, which necessitates RF phased arrays and multiple antennas integrated on the same die. Integration of antennas onto the same die as the phased array and other electronics presents a test challenge since the output is combined in the air and no longer can be separated by physically connecting to the test equipment. This paper presents a novel contact-less test method for measuring the gain and phase mismatch of RF phased array antennas. The proposed method is based on using fully characterized receiver antennas to capture the combined EM output of the transmitter antennas. Near-field analysis is applied with a decoupling approach to determine both gain and phase mismatches so they can be calibrated in the baseband. Near-field measurements are preferable in the production test environment since they do not require large physical distances to be implemented on the load board. A phased array consisting of two elements is modeled and evaluated in near field to verify our test method.

This paper presents an architecture for receiver echo cancellation using in-field self-calibration to enable reception of weak signal generated by implanted passive neuron recorders. The echo cancellation enables the use of passive implant transmitter, resulting in low power consumption, and avoids the need for batteries and charge-storage devices at the implant site. A passive, double balanced diode-based mixer architecture is used for the implant transmitter that directly modulates the received carrier with the neuron sensor signal. The transmitted signal is weak compared to the echo that stems from the reflection from the human skull. An echo cancellation scheme is added to the receiver path to suppress the reflected power at transmitted frequency. A built-in-self calibration module defines the characteristic of the cancelling path for each communication cycle. The air gap between transceiver and the brain is assumed to be around 5mm, but variable from measurement to measurement. A receiver with a sensitivity of -123.55 dBm is designed. According to simulations, a neuron potential as low as 27 μVp-p is detectable with an ideal canceller. The echo signal is canceled up to 200 dB for an ideal canceller. The tolerable error for non-ideal canceller is investigated and compared with the ideal case.

Embedded power regulators, such as low dropout regulators (LDOs), are generally tested for DC behavior and are rarely characterized dynamically. However, LDO loop dynamics play an important role in the overall behavior of the system. Dynamic characterization of LDOs based directly on LDO specifications requires measurement of output transient response with a step input at various points in the circuit. Such characterization is both difficult and costly. Alternatively, LDOs can be characterized by measuring loop dynamics in the form of a transfer function. Since the system is highly non-linear, transfer function can be characterized around a given operating point in terms of poles and zeros. The stability of the system can be inferred from the loop transfer function. This indirect characterization is more feasible but may result in test escapes. In this paper, we investigate the dynamic LDO characterization by closed loop transfer function and evaluate the test coverage with respect to modeled faults in the circuit. We show that faults that are not detectable with DC tests only become detectable with dynamic testing. We also show that the majority of undetectable faults are redundant with regards to the overall operation in terms of step response.

This paper presents a built-in self-test (BIST) system for Low-Dropout Regulators (LDO). Since the LDO is a closed-loop system, stability is a very important but oft-untested parameter for embedded LDOs. The proposed BIST system can measure stability-related parameters by performing cross correlation between an input pattern mimicking noise in the form of Pseudo Random Binary Sequence (PRBS) and the LDO output. In the proposed BIST system, PRBS is injected at the reference voltage input and a mixed-signal correlator is designed for multiplication and integration at the LDO output. A digital controller is designed to shift the PRBS sequence to enable cross-correlation and generate the required control signals. BIST circuit measures the impulse response in the time domain. LDO stability parameters, such as phase margin, can be calculated based on the impulse response. The proposed LDO BIST and an associated LDO as the design under test (DUT) are designed using GlobalFoundries 40nm process. Post layout simulations are performed in order to verify the functionality and performance of the BIST circuit. Post layout simulations show that the proposed BIST circuit can be used to measure the stability parameter with high accuracy. In addition, the proposed BIST has very low overhead.

Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges regarding circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, to extract particular Vdd/fmaxbehavior of the device under test (DUT). Consequently, the test cost associated with frequency binning and the fmaxsearch is significant. This cost is further increased for chips that support dynamic voltage scaling, necessitating the calibration of fmaxat multiple Vddlevels. In order to reduce this burden, we propose an adaptive statistical technique to reduce the fmaxsearch space across multiple Vddlevels by reusing the information previously obtained from the DUT during test-time. The proposed solution employs statistical relations between the speed of the ring oscillators sensitive to different process parameters and speed of the DUT as well as the correlation between the DUT speeds at multiple Vddlevels in improving the prediction of the DUT's fmax. The proposed adaptive solution reduces the test/characterization time and cost at no area or test overhead; such an approach is being explored for the first time to the best of our knowledge. Experiments on a set of ISCAS benchmarks show up to 8x improvement in adaptively reducing the search space for fmaxat multiple Vddlevels.

This article presents a Built-in self-test (BIST) solution for polar transceivers with low cost and high accuracy. Radio frequency (RF) Polar transceivers are desirable for portable devices due to higher power efficiency compared to traditional RF Cartesian transceivers. Unfortunately, their design is quite challenging due to substantially different signal paths that need to work coherently to ensure signal quality. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude. In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion, which leads to violation of spectral mask requirements. Typically, these parameters are not directly measured but calibrated through spectral analysis using expensive RF equipment, leading to lengthy and costly measurement/calibration cycles. However, characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. In this article, we propose a technique to measure with the intent to calibrate impairments of the polar transceiver in the loop-back mode. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments accurately.

Flexible systems that can conform to any shape are desirable for wearable applications. Over the past decade, there have been tremendous advances in the domain of flexible electronics which enabled printing of devices, such as sensors on a flexible substrate. Despite these advances, pure flexible electronics systems are limited by poor performance and large feature sizes. Flexible hybrid electronics (FHE) is an emerging technology which addresses these issues by integrating high performance rigid integrated circuits and flexible devices. Yet, there are no system-level design flows and algorithms for the design of FHE systems. To this end, this paper presents a multi-objective design algorithm to implement a target application optimally using a library of rigid and flexible components. Our algorithm produces a set of Pareto frontiers that optimize the physical flexibility, energy per operation and area metrics. Simulation studies show a 32× range in area and 4× range in flexibility across the set of Pareto-optimal design points.

Wireless Revolution V.2 in the form of Internet of Things (IoT) necessitates development of RF on rapidly evolving manufacturing processes using a small team of engineers. These processing nodes are tuned for digital performance and typically present with higher process variations. Manufactured RF devices either need to include larger margins to guarantee performance or be tuned post-manufacture to recover the performance. In this paper, we present a set of design principles for RF devices that can be adapted post-production for specific needs of the target application. Post-production tuning lifts the design burden from engineering efforts to measurement and calibration at the production test time.

Built-in Self-Test (BIST) is essential, particularly for radio frequency (RF) devices where off-chip RF signal analysis is costly or in some cases, infeasible. Two major problems have made RF BIST elusive. First, process variations make the BIST circuit behavior hard to predict, limiting accuracy of measurements. Second, the overhead, particularly in terms of performance degradation, make RF BIST undesirable. In this paper, we address these two issues for RF BIST gain measurement. First, we show that by setting up relative gain measurements and carefully crafting the BIST methodology and the matching BIST circuit, the effect of process variations on measurement accuracy can be suppressed. Second, by co-designing the BIST circuit together with the device under test (DUT), performance impact can be eliminated or significantly reduced. To demonstrate the proposed approach, we design a low noise amplifier (LNA) as the DUT together with the BIST circuit. We also design a stand-alone LNA with the same specifications and manufacture these two circuits on the same die. We show that the LNA gain can be determined very accurately, using only DC measurements, and the performance impact of the BIST circuit is negligible.

Traditionally, test patterns that are generated for a given circuit are applied in an identical manner to all manufactured devices until each device under test either fails or passes each test. With increasing process variations, the statistical diversity of manufactured devices is increasing, making such one-size-fits-all approaches increasingly inefficient. Adaptive test techniques address this problem by tailoring the test decisions for the statistical characteristics of the device under test. In this article, we present several adaptive strategies to enable adaptive unknown bit masking for faster-than-at-speed testing so as to ensure no yield loss while attaining the maximum test quality based on tester memory constraints. We also develop a tester-enabled compression scheme that helps alleviate memory constraints further, shifting the tradeoff space favorably to improve test quality.

RC and single-inverter-based rail clamps are widely used in semiconductor products for electrostatic discharge (ESD) protection. We propose a technology-node-independent design methodology for these rail clamp circuits that takes process, voltage, and temperature variations into consideration. The methodology can be used as a cookbook by the designer or be used to automate the entire design process. Tradeoffs between various design metrics such as ESD performance (Human Body Model), leakage, and area are considered. Simplified circuit models for the rail clamp are presented to gain insights into its working and to size the circuit components. A rail clamp for core power domain is designed using the proposed approach in 40nm low-power process and performance results of the design are also presented. The effectiveness of the design methodology is proven in three different technology nodes by comparing the obtained design with the best design from among 250,000 designs obtained by randomly sampling from the design space.

Failure due to aging mechanisms in CMOS devices is an important concern of RF circuits. Lifetime of analog/RF circuits is defined as the point where at least one specification will fail due to aging effects. In this brief, we present a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices and inductors at design time (presilicon). We identify reliability hotspots and concentrate on these circuit components to enhance the lifetime with low area and no performance impact.

We propose a self-test method for zero-IF radio frequency transceivers using primarily loopback, aided by a small built-in self-test (BIST) circuitry, to determine critical performance parameters, such as I/Q imbalance and nonlinearity coefficients. The transceiver is placed in the loopback mode by couplers, specifically designed to be asymmetric with respect to the primary path and the BIST path. The loopback path is also designed to include two traces with slightly different delays to enable parameter deembedding. Transceiver parameters are analytically computed using baseband I and Q signals over two frames, each of which is 200 μs in duration. Overall, measurement time is <;10 ms, including computation time. In addition to loopback hardware support and the associated parameter deembedding methodology, we propose a complimentary BIST circuit to measure the transmitter (TX) gain. The measured parameters can be used for predistortion or postdistortion to calibrate the transceiver, both at production time and in the field. Both simulation and hardware measurement results show that the proposed method can determine the target performance parameters with adequate accuracy for digital calibration. Measurement and the subsequent calibration are shown to reduce TX error vector magnitude more than fivefold, even for significantly impaired systems.

A comparator-based rail clamp for handling electrostatic discharge (ESD) events is presented. The new circuit technique allows the use of a time constant that can be much smaller than a traditional RC and inverter-based clamp. The new clamp is more area-efficient and dissipates ESD events with little residual energy. The design is able to support applications with power-ON time slower than 4 μs, is immune to latch-ON, and recovers very quickly if falsely triggered. Experimental results and performance comparisons with the traditional circuit are presented.

RF Built-in-Self-Test requires generation and analysis of high frequency signals on-chip, which usually involves complex circuitry. Generally a high frequency to low frequency conversion, such as a peak or amplitude detector, is employed to analyze the output of the device under test (DUT). However, this conversion circuit is subject to similar process variations as the DUT, which has to be included in the measurement process. Moreover, despite affecting the accuracy of the entire measurement, the input generation for RF BIST is sparsely discussed. While relative measurements, such as gain, can be made without knowing the input signal attributes, other parameters, such as output power, IIP3, or IIP5 require absolute measurements, hence the knowledge of the input signal amplitude. In this paper, we propose a technique for on-chip amplitude measurement that is independent of process variations. The approach relies on on-chip generation of a square wave using an RF limiter with two different amplitudes. Using these two input signals and mathematical modeling, we extract the amplitude at the output of the DUT with high accuracy. The circuits for the BIST have been designed and simulated at the transistor level, including process variations. The concept of the proposed measurement technique is demonstrated in hardware using off-the-shelf components.

An RF Phased array can steer the direction of the beam electronically and it brings about benefits in terms of signal to noise ratio (SNR) and directivity. However, testing the phased array generally requires expensive and high performance RF equipment. This increases production test cost and hampers in-field calibration. We present a low-cost, self-compensating Built-In Self-test (BIST) and calibration solution for RF phased arrays. In our proposed method, we apply a sinusoidal test signal with unknown amplitude to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. The BIST circuits are designed and post layout simulations are performed with within-die and die-to-die process variations. Simulations confirm that the BIST circuit provides very accurate results without having to know sinusoidal signal amplitudes or the relation between them. Furthermore, a prototype four-element phased-array PCB was designed and fabricated for verifying our proposed method. With the proposed method, the phase difference between elements can be measured and calibrated with less than 1° error, which would allow for self-monitoring in 6-bit phased array applications.

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are also subject to higher process variations jeopardizing stable operation of the power supply. This paper presents a technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal energy being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the-shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.

With increasing diversity of supply chains from design to delivery, there is an increasing risk of unauthorized changes within an IC. One of the motivations for this type change is to learn important information (such as encryption keys, spreading codes) from the hardware and pass this information to a malicious party through wireless means. In order to evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this paper, we present a stealth circuit for unauthorized transmissions which can be hidden within the legitimate signal. A CDMA-based spread spectrum with a CDMA encoder is implemented with a handful of transistors. We show that the unauthorized signal does not alter the circuit performance while being easily detectable by the malicious receiver.

BIST for analog and RF circuits has been proposed many years ago and we are still chasing it. One school of thought is to have generic BIST components for input stimulus generation and output analysis and to use them in a plug-and-play fashion. Another school of thought is to develop dedicated circuits for each functionality and re-use the same blocks for the same functionality. A third approach is designing completely circuit-specific BIST for each primary circuit. The truth is ad-hoc examples of BIST have been around for years. However, there is no standardized way of implementing or inserting BIST for analog and RF circuits. The panelists, all experts in this domain, will share their view of the best way of implementing BIST for analog and RF circuits, if there is such a thing…

Globalization of the integrated circuit design and manufacturing flow has successfully ameliorated design complexity and fabrication cost challenges, and helped deliver cost-effective products while meeting stringent time-to-market requirements. On the flip side, it has resulted in various forms of security vulnerabilities in the supply chain that involves designers, fabs, test facilities, and distributors until the end-product reaches customers. One of the biggest threats to semiconductor industry today is the entry of aged, reject, or cloned parts, that is, counterfeit chips, into the supply chain, leading to annual revenue losses in the order of billions of dollars. While traceability of chips between trusted parties can help monitor the supply chain at various points in the flow, existing solutions are in the form of integrating costly hardware units on chip, or utilizing easy-to-circumvent inspection-based detection techniques. In this article, we propose a technique for adaptive unique ID generation that leverages process variations, enabling chip traceability. The proposed method stimulates digital chips with an analog signal from the supply lines, which serve as primary inputs to each gate in the signal path. Using a sinusoidal signal that exercises the transistors as gain components, we create a chip-specific response that can be post-processed into a digital ID. The proposed technique enables quick and cost-effective authenticity validation that requires no on-chip hardware support. Our simulation and experimentation on actual chips show that the proposed technique is capable of generating unique IDs even in the presence of environmental noise.

Built-in self-test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to perform radio-frequency signal analysis. Existing on-chip resources, such as power or envelope detectors or small additional circuitry, can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as in-phase and quadrature (IQ) imbalance, and third-order intermodulation intercept point (IIP3) is challenging. Since IQ imbalances are most amenable for digital compensation, their characterization and monitoring are desirable. In this paper, we propose a multistep BiST technique for transmitter IQ imbalance and nonlinearity using a self-mixing envelope detector. We derive analytical expressions for the output signal in linear and nonlinear modes. Using linear mode expression, we devise test signals to isolate the effects of gain and phase imbalances, dc offsets, and time skews from other parameters of the system in low-power mode. Once isolated, these parameters are calculated easily with a few mathematical operations. In the next step, using a higher power test signal, the nonlinear behavior of the transmitter is excited and the IIP3 of the transmitter is computed based on the analytical expressions. Simulations and hardware measurements show that the technique can provide accurate characterization of the path.

Counterfeit ICs have become an issue for semiconductor manufacturers due to impacts on their reputation and lost revenue. Counterfeit ICs are either products that are intentionally mislabeled or legitimate products that are extracted from electronic waste. The former is easier to detect whereas the latter is harder since they are identical to new devices but display degraded performance due to environmental and use stress conditions. Detecting counterfeit ICs that are extracted from electronic waste requires an approach that can approximate the age of manufactured devices based on their parameters. In this paper, we present a methodology that uses information on both fresh and aged ICs and tries to distinguish between the fresh and aged population based on an estimate of the age. Since analog devices age mainly due to their bias stress, input signals play less of a role. Hence, it is possible to use simulation models to approximate the aging process, which would give us access to a large population of aged devices. Using this information, we can construct a statistical model that approximates the age of a given circuit. We use a Low noise amplifier (LNA) and an NMOS LC oscillator to demonstrate that individual aged devices can be accurately classified using the proposed method.

This paper presents a Built-in self-test (BIST) solution for polar transmitters with low cost. Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, they generally require iterative test/measurement/calibration cycles. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. Typically, these parameters are not directly measured but calibrated through spectral performance analysis using expensive RF equipment, leading to lengthy and costly measurement/calibration cycles. Characterization and calibration of these parameters inside the device would reduce the test time and cost considerably. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth, two parameters that can be digitally calibrated, based on the measurement of the output of the receiver in the loop-back mode. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately.

Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and mitigating performance degradation in cross-coupled LC oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We aim at altering degradation patterns of important performance parameters, thereby improving the lifetime of the circuit with low area and no performance impact. We use simulations based on verified aging models to evaluate the monitoring and mitigation techniques and show that the proposed methods can increase the lifetime of the devices with no impact on the initial performance.

Power down leakage (PDL) test is one of the most sensitive tests to verify device integrity during production test. Generally, the PDL current is measured once at the beginning and once at the end of the production test cycle in order to verify that the test process has not degraded device integrity. This current measurement is typically repeated 100 times or more to achieve accurate results. A wide variation in the measurement results usually necessitates additional measurements and averaging. However, without the proper modeling and analysis, repeating the measurement and averaging results alone will not guarantee the accuracy. In this paper, we analyze root causes of the error for the PDL current measurements. Our analysis indicates that while quantization error and thermal noise have negligible impact on the error of the measurements, the instrument accuracy, timing, and temperature based variation are the major contributors to accuracy. We develop a new accuracy model for the PDL current measurement to account for these major contributors. Using this model, we propose a new systematic optimization method for the test process to achieve the desired accuracy without increasing the test time unreasonably. This method and the model are empirically verified with hardware experiments. With hardware experiments we also show that we can reduce the test time nearly 3-fold using the optimized test sequencing strategy.

One of the major problems associated with integrated DC-DC converters used in state of the art Power Management ICs (PMICs) is dynamic performance and stability degradation due to off-chip component and output current variations. A high accuracy built-in self-test (BIST) architecture measuring load inductance and DC resistance (DCR) of DC-DC converters is presented. The DCR measurement of the inductor also enables continuous, lossless average load current sensing of the DC-DC converter across the inductor. Both the BIST circuit and the primary signal chain utilize low analog complexity frequency-domain ΔΣADC. The ΔΣADC decimation filter nulls also provide current ripple cancellation and average current extraction. The BIST module can measure filter inductance values ranging from 3.6μH to 22.3μH range with average 2.0% error and inductor DCR 13mΩto 68mΩ range with average 2.1% error. The average current sensing enabled by the BIST technique achieves current measurement accuracy with average 2.3% error for 0.1A-1A range load current. BIST and current sensing modules occupy less than 6% of total chip area. The BIST circuitry is fabricated and tested with a 12V input, 1V-11.5V output range, for a 3W output power digital DC-DC converter.

Power management units are essential parts in almost every electronic system. PMUs have distinct test and calibration schemes compared to other regular analog circuits since they operate in the large signal mode and the operation heavily depends on the nature of the load. Built-in test and calibration for PMUs is becoming increasingly more common-place due to the challenges posed by increasing process variations, decreasing form factor, and increasingly diverse load conditions. This panel will discuss the challenges related to testing of power management circuits, calibration and built-in test approaches that are currently in place and the way to move forward.

Testing and calibration of MEMS devices require physical stimulus, which results in the need for specialized test equipment and thus high test cost. It has been shown for various types of sensors that electrical stimulation can be used to facilitate lower cost calibration. In this paper, we present an electrical stimulus based test and calibration technique for overdamped spring-mass capacitive accelerometers which require the characterization of stationary and dynamic calibration coefficients. We show that these two coefficients can be electrically obtained.

Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges in terms of circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, in order to extract particular Vdd/fmaxbehavior of the die under test. This paper aims at adaptively reducing the search space for fmaxat multiple levels by reusing the information previously obtained from the DUT during test-time. The proposed adaptive solution reduces the test/characterization time and costs at no area or test overhead.

High test quality can be achieved through defect oriented testing using analog fault modeling approach. However, this approach is computationally demanding and typically hard to apply to large scale circuits. In this work, we use an improved inductive fault analysis approach to locate potential faults at layout level and calculate the relative probability of each fault. Our proposed method yields actionable results such as fault coverage of each test, potential faults, and probability of each fault. We show that the computational requirement can be significantly reduced by incorporating fault probabilities. These results can be used to improve fault coverage or to improve defect resilience of the circuit.

In this paper, we present a method for accurately calculating the Error Vector Magnitude (EVM) of OFDM transmitters based on their IQ mismatch, IIP3, noise, AM/AM and AM/PM distortion. The effects of these impairments are correlated. Thus, modeling and analyzing them in isolation results in large errors. We derive the analytical relation of the received symbol when all types of impairments are present at once and compute EVM based on this overall relation. This method helps test engineers to compute the EVM based on already measured parameters and eliminates the need to develop and set-up EVM measurements. Simulations and hardware measurements show that this calculation can be done with less than 1% error for a large range of EVM values. This error level has been shown to be within the uncertainty bounds of EVM measurements.

Manufactured devices have a diverse performance/quality profile due to process variations. Devices with superior performance and quality are of higher value while the rest can be sold for a lower price. Separating manufactured devices according to their performance is defined as quality/performance binning and is a very effective way of lowering average device cost. In this manner, devices that have below average quality are not wasted and therefore device cost is reduced. Quality binned devices share the same design and typically go through the same manufacturing process and even the same test process. After the testing step, they are binned according to different sets of performance criteria, typically according to the customer specifications. The bin a device falls depends on the process and typically does not match the amount requested by the customers because of uncertainty (variation) of the process. In this work, we present a multi-bin quality-oriented adaptive test method that efficiently classifies the devices according to the desired quality criteria and minimizes the overall test time.

In this paper we present a self-test method for RF transceivers to determine IQ imbalance, time skews, IIP3, IIP5, AM/AM, and AM/PM distortion with no hardware overhead. The analysis is done through the loop-back set-up over two frames, each of which is 200us in duration. The overall measurement time is less than 10ms including the computation time. The determined parameters can be used for digital calibration, which greatly enhances reliability and yield by widening the tolerance of the parameters. We show through hardware measurements that the target performance parameters can be determined accurately and the EVM can be reduced more than 5 folds, making even highly impaired systems usable. The only additional component to enable our approach is an attenuator in the loop-back path, which can be placed outside the chip. Hence, we call this self test and calibration approach a zero overhead approach.

Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, the difference in architecture results in differences in potential circuit impairments/fault models, leading to different test/measurement/calibration requirements. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create inter modulation distortion that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. Therefore, measurement and compensation/calibration of these parameters are important to ensure proper operation for the polar transmitter. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth based on the measurement of the 3rdorder inter modulation distortion (IMD3) at the output of the transmitter. First, a two-tone input at a sufficiently low frequency is applied to the transmitter baseband input to calculate the delay. Then, we apply another two-tone input at a relatively higher frequency to determine the envelope bandwidth. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately within 10ms which is negligible compared to signal source switching and settling times.

Efficiency of test compaction is very important for production test time minimization. Poor test compaction methods either result in long test time or low test quality for analog and mixed-signal circuits. One of the most important factors in test compaction quality is accuracy of the representation of process statistics. Accurate representation is challenging since process characteristics are not stationary; thus, they need to be updated to maintain a reliable test quality level over the complete production run. Previous work in test compaction either does not take process shift into account or uses simplistic updating methods to avoid the cost of process relearning. In this paper, we propose an efficient relearning method that tracks changes in the process state of devices and generates a compact test list using relearned information for production test. The focus of this paper is production test of packaged devices. We model the mechanics of the process shift with a transformation function. We use information from a set of packaged devices of a reference (characterized) wafer to predict the characteristics of devices coming from other wafers using a very small number of learning samples. Fitting the transformation function enables us to map outdated process information to the up-to-date process information. We demonstrate the performance our method and compare it with previously published work using large scale production data of two distinct mixed-signal circuits. We show that our method maintains superior DPPM levels over large numbers of wafers and lots.

We present an adaptive test flow for mixed-signal circuits that aims at optimizing the test set on a per-device basis so that more test resources can be devoted to marginal devices while passing devices that are not marginal with less testing. Cumulative statistics of the process are monitored using a differential entropy-based approach and updated only when necessary. Thus, process shift is captured and continuously incorporated into the analysis. We also include provisions to identify potentially defective devices and test them more extensively since these devices do not conform to learned collective information. We conduct experiments on an low-noise amplifier circuit in simulations, and apply our techniques to production data of two distinct industrial circuits. Both the simulation results and the results on large-scale production data show that adaptive test provides the best tradeoff between test time and test quality as measured in terms of defective parts per million.

Loop-back is a desirable test set-up for RF transceivers for both on-chip characterization and production testing. Measurement of IQ imbalances (phase mismatch, gain mismatch, DC offset, and time skews) in the loop-back mode is challenging due to the coupling between the receiver (RX) and transmitter (TX) parameters. We present an analytical method for the measurement of the imbalances in the loop-back mode. We excite the system with carefully designed test signals at the baseband TX input and analyze the corresponding RX baseband output. The derived and used mathematical equations based on these test inputs enable us to unambiguously compute IQ mismatches. Experiments conducted both in simulations and on a hardware platform confirm that the proposed technique can accurately compute the IQ imbalances.

Traditionally, test patterns that are generated for a given circuit are applied in an identical manner to all manufactured devices. With increasing process variations, the statistical diversity of manufactured devices is increasing, making such one-size-fits-all approaches increasingly inefficient, and resulting in yield and quality loss. Adaptive test techniques address this problem by tailoring the test decisions for the statistical characteristics of the device under test. In this paper, we present several adaptive strategies to enable adaptive unknown bit masking so as to ensure no yield loss while attaining the maximum test quality based on tester memory constraints.

Increasing integration packs more functionality in a single chip necessitating the testing of even more specification parameters. However, there is a tendency to keep test time budged constrained, which leads test engineers to seek more efficient test strategies. Statistical test compaction methods offer generic and circuit independent means of achieving efficient testing. Adaptive test methodologies have been shown to achieve better test quality versus test time trade-off compared to non-adaptive methods. In this work, we propose a new adaptive test approach geared for multi-site applications to achieve a significantly better test time/test quality trade-off. We employ an innovative compound-device approach that enables us to exploit device-to-device correlations. Moreover, we use neighbor device statistics for efficient defect screening. We show that despite the constraints imposed by multi-site testing, we successfully reap the benefits of adaptive testing in a multi-site environment.

Increasing process variations result in increasing statistical diversity in manufactured devices. Test plans that are developed without this diversity in mind are bound to result in poor test quality/yield and/or long test times. Adaptive testing is a general term that is used to tailor the test strategy to accommodate a wide range of variation in the statistical characteristics of manufactured devices. In this paper, we provide a review of the key works in both digital and analog domains.

Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance is challenging. Since these parameters are most amenable for digital compensation, their characterization and monitoring are desirable. In this paper, we propose a BiST technique for transmitter IQ imbalance using a self-mixing envelope detector. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, and time skews from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances.

Testing radio frequency (RF) transceivers requires the measurement of a diverse set of specifications, requiring multiple testing setups. This complicates load board design, debug, and diagnosis, as well as results in long testing time. In this paper, we present a single setup testing solution for orthogonal frequency-division multiplexing systems RF front-ends based on a loop-around scheme. With this technique, it is possible to determine gain and phase mismatch, inphase–quadrature time skew, and dc offset. Linear gain and IIP3 decouple the transmitter parameters from the receiver parameters. Although loop-around has been used in many forms, the basic challenge is to determine what input conditions will lead to accurate measurement and what form of modeling will yield this accuracy. To this end, we develop test signal design and multistep extraction techniques. Experimental results indicate that IIP3 can be extracted with 0.6 dB maximum error while phase mismatch and gain mismatch can be extracted with 0.3$^{\circ}$and 0.6% maximum error. Our method is able to de-embed the characteristics of transmitter from those of receiver while it requires the analysis of only low-frequency digital baseband signals (I and Q branches) and eliminates the need for RF testers.

In this paper, we propose an adaptive test strategy that tailors the test sequence with respect to the properties of each individual instance of a circuit. Reducing the test set by analyzing the dropout patterns during characterization and eliminating the unnecessary tests has always been the approach for high volume production in the analog domain. However, once determined, the test set remains typically fixed for all devices. We propose to exploit the statistical diversity of the manufactured devices and adaptively eliminate tests that are determined to be unnecessary based on information obtained on the circuit under test. Test time information is incorporated in the method to yield short test time. The proposed methodology is computationally efficient and imposes very little overhead on the tester. We compare our results with other similar specification-based test reduction techniques for a low noise amplifier (LNA) circuit and an analog industrial circuit. Results show 85% test quality improvement for the same test time or 24% test time reduction for the same test quality for the LNA circuit. Moreover, near zero defective parts per million is achieved for the industrial circuit.

Error Vector Magnitude (EVM) is a system-level parameter that is specified for most advanced communication standards. EVM measurement often takes extensive test development efforts, tester resources, and long test times. Since EVM is analytically related to system impairments, which are typically measured in a production test environment, it can be eliminated from the test list if the relations between EVM and system impairments are derived in a manner that is independent of the circuit implementation and manufacturing process. In this paper, we focus on the WLAN standard, and derive the relations between EVM and three of the most detrimental impairments for QAM/OFDM based systems: IQ imbalance, non-linearity, and noise. Simulations and hardware experiments show that the accuracy of the analytical models is in par with a direct EVM measurement with a reasonable test time.

Circuit reliability is an increasingly important concern. Most of the reliability studies have concentrated on digital circuits, which have typically led analog circuits in terms of technology node. This is no longer true as both RF/analog and digital components are being integrated with the leading edge manufacturing process. In this paper, we present a methodology for analyzing the parametric degradation caused by electromigration in inductors and vias at design time. We identify reliability hot spots and concentrate our efforts on these circuit components to enhance the lifetime of the circuit with low area and no performance impact.

Defective Parts Per Million (DPPM) is an important quality metric that indicates the ratio of defective devices shipped to the customers. It is necessary to estimate and minimize DPPM in order to meet the desired level of quality. However, DPPM estimation requires statistical simulations, which are computationally costly if traditional methods are used. In this work, we propose an efficient DPPM estimation method for analog circuits that greatly reduces the computational burden. We employ a model based approach to selectively simulate only consequential samples in DPPM estimation. We include methods to mitigate the effect of model imperfection and robust model fitting to guarantee a consistent and efficient estimation. Experimental results show that the proposed method achieves 10xto 25x reduction in the number of simulations for an RF receiver front-end circuit.

Outlier devices behave differently from the majority of the devices and are considered to be potentially defective. Identifying outliers has many applications in test, including defect filters for alternate test, and setting pass/fail limits for automotive domain. In previous work, outliers have been identified using single dimensional and/or static methods which does not exploit information efficiently. In this work, we propose an adaptive multidimensional outlier analysis method that combines the information of multiple measurement parameters and judiciously selects only information rich parameters to maximize detection probability. Furthermore, the proposed method continously updates to track process shift to enable adaptation to the evolving processes. The proposed method can be integrated within an existing test framework to improve test quality with little or no additional test time cost. In this context, we integrate our technique with an adaptive test framework and show that the method enables improved test quality.

Analog fault modeling (AFM) provides a quantitative measure of quality and insight into defective device behavior. However, the high computational burden typically associated with fault simulation makes it unappealing for industrial applications. We propose an efficient methodology to reduce computational burden of the AFM method by exploiting the hierarchical nature of process variation. We apply the proposed methodology on an industrial SerDes TX Driver circuit and achieve 98% simulation time reduction. We quantify defect impact with a defect severity measure.

In this letter, we present a 2x-site test solution for radio frequency transceivers using only baseband signals for analysis. We perform all operations on communication standard-compliant signal packets, thereby putting the device under the normal operating conditions. The transmitter on one device under test (DUT) is coupled with a receiver on another DUT to form a complete transmitter-to-receiver path. Parameters of the two devices are decoupled from one another by carefully modeling the system and using signal processing techniques. Simulation as well as measurement results confirm the high accuracy of the proposed technique.

Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

Despite their small size, analog/mixed-signal circuits start with an extensive set of parameters to test for. During production ramp up, most of these tests are dropped using statistical analysis techniques based on the dropout patterns. While effective in reducing the number of tests, this approach treats each device in an identical manner. As the statistical diversity of the devices increases due to increasing process variations, such homogeneous testing approaches may prove to be inefficient. After a number of initial measurements, device-specific information is available, which can provide clues as to where in the process space that device falls. Using this information, the test set for each device can be tailored with respect to its own statistical information. In this paper, we present an adaptive test flow for mixed-signal circuits that aims at optimizing the test set per-device basis so that more test resources can be devoted to marginal devices whereas devices that fall in the middle of the process space are passed with less testing. We also include provisions to identify potentially defective devices and test them more extensively since these devices do not conform to learned collective information. We conduct experiments on an LNA circuit in simulations and apply our techniques to production data of two distinct industrial circuits. Both the simulation results and the results on large-scale production data show that adaptive test provides the best trade-off between test time and test quality as measured in terms of defective parts per million.

Multiple-input-multiple-output (MIMO)-based systems are extremely popular as they offer data rates as twice as fast as currently available systems. Their testing becomes more complicated due to the increased number of RF paths. This increases the overall test cost of these devices both in terms of test time and instrumentation cost. In this paper, we demonstrate a low cost MIMO test solution which targets critical specifications that are fundamental to the MIMO system operation, such as gain, IIP3, and phase imbalances between the RF paths. Our test methodology measures these parameters with a single test setup that enables the calculation of these performance parameters. Using the proposed test method, RF MIMO systems can be tested using a mixed signal tester, and on-board circuitry within a reasonable accuracy. Both simulation and measurement results confirm the high accuracy and repeatability of our test technique.

The impact of impairments such as transmitter/receiver I/Q gain/phase mismatch on the performance have become severe due to high operational speeds and continuous technology scaling. In this paper, we present a built-in-self-test (BiST) solution for quadrature modulation transceiver circuits using only transmitter and receiver baseband signals for test analysis. The mapping between transmitter input signals and receiver output signals are used to extract impairment and nonlinearity parameters separately with the help of the NLS method and detailed nonlinear system modeling. Experimental measurement results are in good agreement with the simulations and they confirm the high accuracy of the proposed method.

In this paper, we propose an adaptive test strategy that tailors the test sequence with respect to the properties of each individual instance of a circuit. Reducing the test set by analyzing the dropout patterns during characterization and eliminating the unnecessary tests has always been the approach for high volume production in the analog domain. However, once determined, the test set remains typically fixed for all devices. We propose to exploit the statistical diversity of the manufactured devices and adaptively eliminate tests that are determined to be unnecessary based on information obtained on the circuit under test. We compare our results with other similar specification-based test reduction techniques for an LNA circuit and observe 90% test quality improvement for the same test time or 24% test time reduction for the same test quality.

Alternate RF testing is a very promising candidate for replacing the costly standard specification-based approach. The defect filter in the alternate test flow is a crucial preparatory step for the overall success of alternate test. In this paper, we present a novel nonlinear defect filter based on an estimate of the joint probability density function of the alternate measurements. The construction of the filter does not require a defect dictionary and can accommodate any underlying density without needing any prior knowledge regarding its parametric form.

Analog circuits are often tested based on their specifications. While specification-based testing ensures the initial product quality, full testing is often not possible in high volume production. Moreover, even full specification-based testing cannot guarantee that the circuit does not contain any physical defects. Some application domains require near-zero defect levels independent of whether the specifications are met. In this work, we present a defect based test optimization method focusing on defective parts per million (DPPM) minimization. We extract potential defects through inductive fault analysis (IFA) and reduce the number of tests without degrading the test quality. In order to achieve near zero DPPM, we employ outlier analysis to identify defective circuits that cannot be identified using specification based methods. Simulation results on an LNA show that DPPM is reduced down to 0 at a cost of 0.2% yield loss with the proposed method.

In this paper, we present a technique to enable accurate built-in measurement of EVM for OFDM transceivers. This measurement technique only relies on the decoded bit pattern, and does not require any additional test equipment. In order to accurately predict EVM without using analog signal analysis, we intentionally code more symbols into the bit pattern in test mode, which enables the decoding of IQ signals in finer granularity. We present an innovative DFT technique to measure EVM on-chip with very little overhead. We also provide an analytical framework to determine how the DFT technique needs to be implemented. Experimental results using MATLAB simulations and hardware measurements confirm the accuracy of the proposed technique.

In this paper, we present a 2x-site test solution for GSM transceivers using only baseband signals for analysis. We perform all operations on standard-compliant GSM packets, thereby putting the device under the normal operating conditions. The transmitter on one device under test (DUT) is coupled with a receiver on another DUT to form a complete Tx-Rx path. Parameters of the two devices are decoupled from one another by carefully modeling the system into a known format and using signal processing techniques. Simulation as well as measurement results confirm the high accuracy of the proposed technique.

Due to the increasing complexity of radio-frequency circuits, their testing becomes more challenging. A large number of performance parameters under several operation conditions are needed in order to ensure compliance to specifications. In this paper, we present a low-cost test methodology that determines significant performance parameters, such as path gainIIP3, quadrature imbalances, noise, bit error rate, and error vector magnitude through a single test setup. The proposed test methodology is applicable for both single-carrier and multicarrier systems. Simulation and measurement results indicate that these performance parameters can be calculated and estimated accurately through a single test setup and using a shorter test sequence than required by traditional techniques. In addition, a calibration technique is presented for single-carrier systems to recover marginally failing devices through analytically correcting performance parameters.

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of ldquobig-D/small-Ardquo mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal ldquobig-D/small-Ardquo SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.

In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method.

We present a diagnosis methodology for assembly failures in RF front-end circuits embedded in System-in-Package (SiP) designs. We focus on technologies where nonlinear components reside on several active dies and the linear components reside on a passive base. While there can be many pin connections between the base and the active die in these designs, there are only a few outside pins available. We present a systematic analysis technique to select viable test conditions to distinguish among the faults. Normal operation mode as well as non-functional mode test signals are used to increase the diagnostic resolution. We show that most assembly faults can be distinguished from one another using non-functional mode test signals on a generic LNA circuit. We also apply our technique to a commercial tuner for a subset of representative faults and reach the same conclusions.

Characterization of RF ICs based on their error vector magnitude (EVM) is gaining a lot of attention in the industry. In order to deliver this specification at a reasonable cost, the input test signal and the analysis techniques have to be optimized such that EVM testing can provide a robust pass/fail decision while utilizing a reasonable amount of tester resources. In this paper, we propose techniques to optimize EVM testing, both from input signal generation and from output analysis perspectives. Our goal is to achieve both efficient and reliable test approaches for WLAN (Wireless Local Area Networks) circuits.

This paper presents a loop-back method for quadrature modulation transceiver circuits to diagnose parametric faults of the system, such as I/Q mismatch, baseband/RF time skew, and DC offsets. The proposed method is capable of separating the transmitter parameters from the receiver parameters in a single measurement. Digital baseband signals are used as test input and the received I/Q baseband signals are analyzed for parameter extraction. Experimental results show that the test method has 1.5% RMS error performance in the presence of thermal noise and unknown delays caused by the loop-back connection. The test technique can easily be implemented on a digital tester. Either on-chip baseband data converters or load board data converters (for transceiver circuits without digital output) can be used for interfacing the transceiver circuit under test.

Radio-frequency (RF) test cost is soaring due to the increasing complexity of RF devices. Radically new test approaches that enable test time reduction while ensuring product quality are needed to reduce the overall product cost. In this paper, we present a test development methodology for RF circuits based on novel parametric, open-circuit, and short-circuit defect models. We inject parametric defects as deviations in physical circuit parameters, such as resistances, transistor widths, and lengths, and inject open- and short-circuit defects into the critical locations that are derived from the layout using inductive fault analysis. Despite fault injection, we consider a circuit unacceptable only if it violates any one of the performance specifications. Our test development method aims at reducing not only the number of measurements but also the overall test hardware cost by incorporating the relative setup cost of each measurement into our selection criteria. Experimental results on an RF front-end device show that our test methodology reduces the test time by 50% and the number of test setups by 17% while identifying all unacceptable circuit instances with a 99% failure coverage without any yield loss.

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this article, we present a hierarchical variance analysis methodology for multistage analog circuits. Starting from the process/layout level, we derive implicit hierarchical relations and extract the sensitivity information analytically. We make use of previously computed values whenever possible so as to reduce computational time. The proposed approach is particularly geared for the domain of design and test automation, where multiple runs on slightly different circuits are necessary. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of "big-D/small-A" mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging costs. Experimental results are presented for a typical mixed-signal "big-D/small-A" SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.

This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysis method is an alternative to histogram based analysis techniques to provide test time improvements, especially when the resources are scarce. In addition to the measurement of DNL and INL, non-monotonic behavior can also be detected with the proposed technique. We present two implementation options based on how much on-chip resources are available. The ramp generator has a high linearity over a full-scale range of IV and the generated ramp signal is capable of testing 13-bit ADCs. The circuit implementation of the ramp generator utilizes a feedback configuration to improve the linearity having an area of 0.017mm2in 0.5mum process

As radio frequency (RF) devices become more complex, the specifications become more stringent. In order to guarantee successful operation and compliance to certain specifications, digital correction techniques that compensate the device impairments are needed. In this paper, we present an analytical digital in-phase (I) and quadrature (Q) imbalance and non-linear compression correction methodology that improves the system bit error rate (BER). The gain and phase imbalances are corrected by using the gain and phase imbalance test data obtained during the product testing. The non-linear compression term is removed using Newton's method. The proposed test methodology is applicable for both burst based systems and continuous systems. Simulation results indicate that the proposed method improves the BER even under harsh noise contamination. The computational overhead of the compensation technique is minimal.

This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only relevant fault model. The delay fault model - which assumes that the faulty circuit element gets the correct value but that this value arrives too late - encompasses many of the actual in-field wearout faults in modern microprocessors. In-field wearout faults, such as time-dependent dielectric breakdown and electromigration, cause signal propagation delays which may be missed during production test time. These defects progress exponentially over time, potentially causing a catastrophic failure. Our goal is to diagnose hard delay faults (i.e., identify them as hard faults, not transients) during run-time before they lead to catastrophic chip failures. Results show that we can diagnose all injected delay faults and that prior diagnosis mechanisms, which target only stuck-at faults, miss the majority of them.

As radio frequency (RF) devices become more complex and the integration levels increase, their testing becomes more challenging. In order to guarantee successful operation and compliance to certain specifications, measurement of a large number performance parameters under the prescribed operation conditions is needed. Such detailed characterization typically necessitates long test times and expensive instrumentation, increasing the test cost. In this paper, we present a low cost test methodology that determines the RF device's vital performance parameters, such as path gain, IIP3, quadrature imbalances, noise, bit error rate (BER), and error vector magnitude (EVM) through a single test setup. The proposed test methodology is applicable for both single carrier systems and multi-carrier systems. Simulation and measurement results indicate that these performance parameters can be calculated and estimated accurately through a single test set-up and using a shorter test sequence than required by traditional techniques.

Circuit and test yield information provides essential feedback to circuit designers and test engineers to evaluate their designs and test set-ups. Traditionally, Monte Carlo analysis and other sample-and-simulate based approaches have been used for yield estimation. However, such computationally costly techniques cannot be used if yield estimation needs to be repeated multiple times, as in the case of test evaluation. In this paper, we propose a technique to conduct accurate and efficient overall yield estimation based on hybrid quadratic modelling and hierarchical statistical profiling. We also develop compatible models for environmental noise and measurement error, two most important error sources in the test process. Our experiments on a baseband amplifier and a cascaded LNA-mixer circuit confirm that the proposed yield estimation technique achieves significant computational time saving with negligible accuracy loss when used for multiple test set-up evaluations.

Due to process variability which makes the analog circuit response probabilistic, fault simulation effectively requires a statistical analysis for each fault. As a result, fault simulation presents the major computational time component in analog test automation. While recently a number of statistical analysis approaches for analog circuits have been proposed, overall computational time is a big concern when a high number of parametric faults need to be evaluated. We present a series of schemes to increase the efficiency of fault simulation by extracting and reusing information from one fault simulation to another. Experiments on a baseband amplifier circuit confirm that the proposed techniques can be collectively applied to provide about a 50-fold simulation time saving at the cost of less than 3% loss in accuracy when compared with similar prior techniques.

Multiple input multiple output (MIMO) based systems have recently received a lot of attention as their projected data rate is twice as fast as the currently available systems. Due to the increased number of RF paths, the testing becomes more complicated, thereby increasing the overall test cost of these devices. In this paper, the authors propose a low cost MIMO test solution which targets critical specifications that are fundamental to the MIMO system operation, such as gain, IIP3, and phase imbalances between the RF paths. Our test methodology measures these parameters with a single test setup that enables the calculation of the relevant performance parameters. Using the proposed test method, RF MIMO systems can be tested using a mixed signal tester, and on-board circuitry with a reasonable accuracy. Both simulation and measurement results confirm the high accuracy and repeatability of our test technique

We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, we use DIVA dynamic verification to detect and correct errors. Our new scheme for diagnosing hard faults tracks instructions' core structure occupancy from decode until commit. If a DIVA checker detects an error in an instruction, it increments a small saturating error counter for every FDU used by that instruction, including that DIVA checker. A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault. For deconfiguration, we use previously developed schemes for functional units and buffers and present a scheme for deconfiguring DIVA checkers. Experimental results show that our reliable microprocessor quickly and accurately diagnoses each hard fault that is injected and continues to function, albeit with somewhat degraded performance.

The test development efforts for analog circuits today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement setup requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric and catastrophic faults into the circuit and analyzing the masking effect of process variations, we develop a fault injection and simulation technique for analog circuits that is specifically geared toward information reuse. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on several circuits confirm the high accuracy of our variance analysis technique and show a nearly 72% reduction in the number of tests for a three-stage amplifier circuit in the experiment after the application of the test selection algorithm.

The increasing share of test and packaging as a percentage of the overall cost for RF transceivers necessitate, radically test new approaches to both wafer-level and final production testing. We present a new system-level test setup for voltage-controlled oscillator (VCO) modulating transceiver architectures that we call the delayed-RF setup, along with a novel, all-digital design-for-testability (DFT) modification that enables coverage of the most important system-level specifications. The delayed-RF setup can be used during wafer sort, thus preventing the packaging of nonfunctional dies. Based on this setup and the DFT technique, we present an automatic test development methodology for FM transceivers using frequency-domain signature analysis. We develop two distinct pass/fail criteria based on eigensignatures and envelope signatures and a test generation algorithm that aims at minimizing the required delay while attaining full coverage of target faults. We develop a fault injection and simulation platform for a VCO-modulation, low-IF transceiver architecture using MATLAB and behavioral models including nonideal response. The proposed methodology enables the automation of the test generation process, thus reduces the test development time. Experimental results have shown a 90% reduction in the required delay thereby reducing the cost of this test hardware item

As wireless LAN devices become more prevalent in the consumer electronics market, there is an ever increasing pressure to reduce their overall cost. The test cost of such devices is an appreciable percentage of the overall cost, which typically results from the high number of specifications, the high number of distinct test set-ups and equipment pieces that need to be used, and the high cost of each test set-up. In this paper, we investigate the versatility of EVM measurements to test the variable-envelope WLAN (Wireless Local Area Networks) receiver and transmitter characteristics. The goal is to optimize EVM test parameters (input data and test limits) and to reduce the number of specification measurements that require high test times and/or expensive test equipment. Our analysis shows that enhanced EVM measurements(optimized data sequence and limits, use of RMS, scale, and phase error vector values) in conjunction with a set of simple path measurements (input-output impedances) can provide the desired fault coverage while eliminating lengthy spectrum mask and noise figure tests

Multiple input multiple output (MIMO) systems that enable data transfer rates beyond 100 Mbps for WLAN applications is under development and will emerge rapidly. While the higher data rates will enable numerous features in modern communication devices, the industry has to face the soaring test cost due to the increased test complexity and test time. Since MIMO systems have multiple RF paths, each path needs to be individually tested. Moreover, mismatch parameters among the multiple paths require synchronized sampling of RF signals, requiring complicated equipment In this paper, we propose a low cost MIMO test solution that targets the specifications that are fundamental for MIMO operation, such as gain, IIP3, and phase imbalances between the RF paths. Our test methodology measures these parameters with a high accuracy while requiring only one RF frequency synthesizer. Using the proposed test method, RF MIMO systems can be tested using a mixed signal tester and a single fixed frequency RF signal generator.

As one way of reducing the reliance on mixed signal testers for circuits with small analog content, researchers have proposed built-in self-test (BiST) techniques that target specific parameters of analog circuits. Most BiST techniques for phase locked loops (PLL) aim at measuring the timing jitter through precise on-chip clocks and/or additional computation of measured specs. In this paper, we propose a built-in test circuit to perform go/no-go testing for in-band PLL phase noise. Our circuit measures the band-limited, low frequency noise power at the input of the voltage controlled oscillator (VCO) which is translated as the high frequency phase noise at the output of the PLL. Our circuit contains a self calibration sequence based on a simple sinusoidal input to make it robust to process variations. The circuit is implemented using 0.8mum CMOS process with the equivalent area of roughly 800 2-input minimum size NAND gates. Monte Carlo simulations have confirmed that the test circuit can robustly detect noise levels that are above the specified fail level

In this paper, we propose a low-cost fault tolerance technique for microprocessor multipliers, both non-pipelined (NP) and pipelined (P). Our fault tolerant multiplier designs are capable of detecting and correcting errors, diagnosing hard faults, and reconfiguring to take the faulty sub-unit off-line. We utilize the branch misprediction recovery mechanism in the microprocessor core to take the error detection process off the critical path. Our analysis shows that our scheme provides 99% fault security and, compared to a baseline unprotected multiplier, achieves this fault tolerance with low performance overhead (5% for NP and 2.5% for P multiplier) and reasonably low area (38% NP and 26% P) and power consumption (36% NP and 28.5% P) overheads

In this paper, we present a parametric fault diagnosis approach for analog/RF circuits based on a Bayesian framework. The Bayesian fault diagnosis requires extensive statistical profiling which is enabled by a an efficient hierarchical process variability analysis. Both DC and AC parameters are used as measurements to provide maximum diagnostic resolution. A sensitivity guided test input selection scheme is used to determine the measurement attributes that are most likely to distinguish among the faults. Fault dictionaries are constructed using parametric faults at the transistor level that have both marginal and higher deviations. During the diagnosis step, additional online profiling helps increase the diagnostic resolution. Experiments on a transistor level amplifier circuit confirms that the approach is accurate in terms of statistical attributes and most deviations in layout and process level parameters can be correctly diagnosed.

High-frequency linear analog circuits are widely used in high-speed and wireless radio frequency communication circuits as front-end devices. The small-signal model of transistors is typically used to evaluate the bandwidth (BW) of such devices during design iterations. However, since such devices typically push the boundaries of the manufacturing processes, small-signal parameters are not entirely reliable, leading to systematic silicon failures due to inadequate BW. With increasing uncertainties in the modeling and processing of semiconductor devices, it is essential that the sources of BW failures be identified immediately once the devices are manufactured. This paper presents a methodology to diagnose the systematic BW failures in linear broadband analog circuits. The most important small-signal parameters of internal transistors are determined to enable the redesign process. An evolutionary algorithm specifically designed to mimic the expected errors is used to ensure fast convergence to the correct solution. Sensitivity analysis is used to determine the set of the most impactful small-signal parameters and to guide the evolutionary search. A weighed average approach is also used to improve the accuracy for large-scale systems. Experimental results indicate that the proposed algorithm determines the parameters accurately and scales well in terms of accuracy and computation time

We present a concurrent testing methodology for detecting catastrophic faults in digital microfluidics-based biochips and investigate the related problems of test planning and resource optimization. We first show that an integer linear programming model can be used to minimize testing time for a given hardware overhead, for example, droplet dispensing sources and capacitive sensing circuitry. Due to the NP-complete nature of the problem, we also develop efficient heuristic procedures to solve this optimization problem. We apply the proposed concurrent testing methodology to a droplet-based microfluidic array that was fabricated and used to perform multiplexed glucose and lactate assays. Experimental results show that the proposed test approach interleaves test application with the biomedical assays and prevents resource conflicts. The proposed method is therefore directed at ensuring high reliability and availability of bio-MEMS and lab-on-a-chip systems, as they are increasingly deployed for safety-critical applications.

Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.

Increasing process variability necessitates reliable analysis of its effects on circuit performance not only at the top level but also at intermediate levels. Mixed-signal circuits with multiple hierarchical layers, multiple parameters, and complex functional relations are especially susceptible to such variations. In this paper, we present a hierarchical method for process variation analysis. The ability to compute the variance of parameters at each hierarchical layer makes the method particularly suited for helping designers through design iterations. Experimental results indicate that the proposed method achieves high computational efficiency with up to 2% compromise in accuracy even for highly non-linear functional relations.

As device sizes shrink and current densities increase, the probability of device failures due to gate oxide break-down (OBD) also increases. To provide designs that are tolerant to such failures, we must investigate and understand the manifestations of this physical phenomenon at the circuit and system level. In this paper, we develop a model for operational OBD defects, and we explore how to test for faults due to OBD. For a NAND gate, we derive the necessary input conditions that excite and detect errors due to OBD defects at the gate level. We show that traditional pattern generators fail to exercise all of these defects. Finally, we show that these test patterns can be propagated and justified for a combinational circuit in a manner similar to traditional ATPG.

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. We present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.

The test cost of RF systems is an increasing percentage of the overall system cost. This trend is mainly due to the traditional RF testing schemes based on the full measurement of specifications over a wide range of input conditions. In this paper, we present a test development methodology for RF circuits based on a novel parametric fault definition. We target deviations in physical circuit parameters, such as a resistance or the width of a transistor. However, we consider a circuit faulty only if it violates a specification. Our test development method aims at reducing not only the number of measurements, but also the overall test hardware cost by incorporating the relative set-up cost of each measurement into our selection criteria. Experimental results on a low-noise amplifier (LNA) circuit show that our test development technique reduces the overall test time (49%-67%) as well as the number of required measurement set-ups (17%-33%) considerably. By defining the target faults based on specification violations, our technique also provides high confidence in the test quality.

The test development efforts for analog/RF circuits in computer systems today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement set-up requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric deviations into the circuit and analyzing the masking effect of process variations, we develop a hierarchical process variability analysis technique for analog/RF circuits that is specifically geared towards information re-use. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on a differential amplifier circuit confirm the high accuracy of our variance analysis technique and show a 57% reduction in the number of tests after the application of the test selection algorithm.

The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal SOCs reduces test cost. ATWs enable analog test using digital test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three ITC'02 benchmark SOCs that have been augmented with five representative analog cores.

The test cost of RF systems is an increasing percentage of the overall system cost. This trend is mainly due to the traditional RF testing scheme based on measurement of specifications over a wide frequency range. A lower cost alternative is to use defect-based testing for RF circuits. However, the traditional defect models in the analog domain need to be revised to include high frequency effects in the RF domain. In this paper, we present a new defect model for breaks in metal traces to be used for defect-based testing in the RF domain. We present our fault model based on DC, AC, and noise characteristics and provide a case study for a transistor-level RF front-end. We confirm the AC characteristics of the model through EM simulations and compare our detectability results with the results of the resistive open-circuit model traditionally used in the analog test domain. Our study confirms that in many cases the resistive-based open-circuit model yields overly optimistic detectability results for defects in the signal path. We show that targeting particular defects and using their detectability information, the overall test time of RF devices can be reduced appreciably

We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, we use DIVA dynamic verification to detect and correct errors. Our new scheme for diagnosing hard faults tracks instructions' core structure occupancy from decode until commit. If a DIVA checker detects an error in an instruction, it increments a small saturating error counter for every FDU used by that instruction, including that DIVA checker. A hard fault in an FDU quickly leads to an above-threshold error counter for that FDU and thus diagnoses the fault. For deconfiguration, we use previously developed schemes for functional units and buffers, and we present a scheme for deconfiguring DIVA checkers. Experimental results show that our reliable microprocessor quickly and accurately diagnoses each hard fault that is injected and continues to function, albeit with somewhat degraded performance.

Decreasing profit margins and time-to-market windows for radiofrequency transceivers, rule out the traditional component-based testing and diagnosis methods. Over the past few years, there has been a significant shift in the transceiver test methods towards full-path and loop-back testing. However, the benefits of path-based testing cannot be fully attained unless complimentary diagnosis methods can be developed. In this paper, we present an adaptive diagnosis methodology to identify the failing component in RF receivers. Once the fault type (hard fault or soft fault) is identified using eigensignature correlations, input signals are selected and ambiguity groups determined. A new input signal is applied based on the ambiguity groups until full diagnostic resolution is reached or test inputs are exhausted. While it is typically believed that partitioned parameters, such as the gain of an individual component, cannot be fully diagnosed, the inherently non-linear behavior of analog blocks results in distinguishable response patterns even for scalar parameters. Experimental results confirm that diagnosis using only path-based measurements is viable.

To achieve high reliability despite hard faults that occur during operation and to achieve high yield despite defects introduced at fabrication, a microprocessor must be able to tolerate hard faults. In this paper, we present a framework for autonomic self-repair of the array structures in microprocessors (e.g., reorder buffer, instruction window, etc.). The framework consists of three aspects: 1) detecting/diagnosing the fault, 2) recovering from the resultant error, and 3) mapping out the faulty portion of the array. For each aspect, we present design options. Based on this framework, we develop two particular schemes for self-repairing array structures (SRAS). Simulation results show that one of our SRAS schemes adds some performance overhead in the fault-free case, but that both of them mask hard faults 1) with less hardware overhead cost than higher-level redundancy (e.g., IBM mainframes) and 2) without the per-error performance penalty of existing low-cost techniques that combine error detection with pipeline flushes for backward error recovery (BER). When hard faults are present in arrays, due to operational faults or fabrication defects, SRAS schemes outperform BER due to not having to frequently flush the pipeline.

In this paper, we present a hardware technique, called self-repairing array structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated "check row". We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.

Recent years have seen the emergence of droplet-based microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating microfluidic components must be tested adequately. In this paper, we investigate test planning and test resource optimization methods for droplet-based microfluidic arrays. We first outline a methodology based on integer linear programming (ILP) that yields optimal solutions. Due to the NP-complete nature of the problem, we develop heuristic approaches for optimization. Experimental results indicate that for large array sizes, heuristic methods yield solutions that are close to provable lower bounds. These heuristics ensure scalability and low computation cost.

With increasing uncertainties in the modeling and processing of semiconductor devices, it is essential that the sources of failures be identified once the devices are manufactured. We present a methodology to diagnose the problems in broadband amplifiers by determining the most important small signal parameters of the internal transistors. We use an evolutionary algorithm specifically designed to mimic the expected errors to ensure fast convergence to the correct solution. Sensitivity analysis is used to determine the set of the most impactful small signal parameters and to guide the evolutionary search. Experimental results indicate the proposed algorithm determines the parameters accurately and it scales well in terms of accuracy and computation time.

Increasing system complexity and test cost demands new system-level solutions for mixed-signal systems. In this paper, we present a testability analysis and DfT insertion methodology for end-to-end mixed-signal paths. Based on behavioral models and path analysis, testability problems in the path are determined and classified in terms of their bottleneck. Possible solutions to each problem are identified. The DfT insertion problem is then formulated as a min-cost set cover problem to achieve the most cost-efficient solution. In experimental results where test point insertion is used as the DfT approach, nearly 50% reduction in the overall DfT overhead is achieved.

We present an automatic test development methodology for FM transceivers based on frequency-domain signature analysis and delayed-RF set up. We develop two distinct pass/fail criteria based on eigensignatures and envelope signatures and a test generation algorithm that aims at minimizing the required delay while attaining full coverage of target faults. We develop a fault injection and simulation platform for a VCO-modulation, low-IF transceiver architecture using MATLAB and behavioral models including non-ideal response. The proposed methodology enables the automation of the test generation process, thus reduces the test development time. Experimental results have shown a 90% reduction in the required delay thereby reducing the cost of this test hardware item.

Traditionally, radio frequency (RF) paths are bypassed during wafer sort due to the high cost of RF testing. Increasing packaging costs, however; result in a need for a more thorough wafer-level testing including the RF path. In this paper, we propose a loop-back architecture, along with a novel, all-digital design-for-testability (DfT) modification that enables cost efficient testing of various defects at the wafer level. These methods are applicable to a wide range of cost-sensitive applications that use the modulation of the voltage-controlled-oscillator (VCO). Experimental results using a Bluetooth platform and considering a variety of defects confirm the viability of the approach.

Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for automatic design of concurrent failure detection circuitry for linear analog systems is discussed in this paper. The desired hardware bound is specified as a constraint; the methodology aims at providing coverage in terms of all the circuit components while minimizing the loading overhead by reducing the number of internal circuit nodes that need to be tapped. Parameter tolerances are incorporated through either statistical or mathematical analysis to determine the threshold for failure alarm.

Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in safety-critical biomedical applications, dependability emerges as a critical performance parameter. In this paper, we present a costeffective concurrent test methodology for droplet-based microelectrofluidic systems. We present a classification of catastrophic and parametric faults in such systems and show how faults can be detected by electrostatically controlling and tracking droplet motion. We then present tolerance analysis based on Monte-Carlo simulations to characterize the impact of parameter variations on system performance. To the best of our knowledge, this constitutes the first attempt to define a fault model and to develop a test methodology for droplet-based microelectrofluidic systems. 1

Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for the automatic design of concurrent failure detection circuitry for linear analog systems is discussed in this paper In contrast to previous approaches, the methodology aims at providing coverage in terms of all the circuit components while minimizing the loading overhead by reducing the number of internal circuit nodes that need to be tapped Parameter tolerances are incorporated through either statistical or mathematical analysis to determine the threshold for failure alarm. Experimental results confirm that full coverage can be attained while keeping the hardware overhead within a pre-specified budget.

Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize onchip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.

As the use of wireless communications in daily life increases, attaining low-cost solutions becomes increasingly important due to shrinking profit margins. Cost optimization that solely targets at minimization of the cost of system architecture may result in suboptimal, highly untestable, solutions. Test design and design for testability need to be incorporated into the system design flow to achieve viable solutions. This paper presents an analysis of test requirements, implications and test cost for low-cost Bluetooth systems. Testability problems are identified and possible solutions along with avenues to reduce the test cost by utilizing lower-cost testers are discussed.

Higher levels of integration, the need for test re-use, and the mixed-signal nature of today's SOC's necessitate hierarchical test generation and system level test composition to meet stringent market requirements. In this paper a novel methodology for testing analog and digital components in a signal path is discussed. Consequent testability analysis can be utilized to reduce DFT requirements, while test translation provides highly effective low cost test. The proposed approach seamlessly propagates test information across the analog/digital divide. Experimental results substantiate the effectiveness of the proposed mixed-signal test synthesis methodology.

Mixed-signal design and test tools are failing to keep pace with the increasing necessity for design exploration in the early stages. We outline a methodology and toolset to enable test selection at the early design stages by providing a high level fault simulator and associated block-level modeling and traversal capabilities. Experimental results show that the outlined methodology provides superior fault simulation speed-ups while helping to minimize the test time for a mixed-signal receiver system.