This paper presents an ultra-low quiescent current power-wise buck converter for portable devices. To achieve high conversion efficiency across a wide range of load currents while minimizing the output ripple, the converter utilizes pulse-width modulation (PWM) and pulse-frequency modulation (PFM) control methods in heavy load and light load conditions, respectively. Time-division power supply technique is implemented to reduce the quiescent current. The converter incorporates an 8-bit built-in digital-to-analog converter (DAC), allowing selection of 256 different output voltages ranging from 0.5V to 1.8V in 5mV steps. Additionally, a transient enhancement circuit is included to expedite the transient response during mode switching. Fabricated in$0.18\boldsymbol {\mu }$m CMOS process, the proposed converter is capable of handling load currents from$1\boldsymbol {\mu }$A to 600mA with an input voltage of 2.5V to 5V. Featuring an ultra-low quiescent current of 55nA, the converter achieves a peak efficiency of 94.1% and maintains greater than 85% efficiency over a load range of$10\mu $A to 500mA when input and output are 3.6V and 1.8V, respectively.

This paper presents a power-efficient fourth-order, 50-MHz active-RC filter with high dynamic range (DR). Unlike conventional Tow-Thomas biquads, the proposed design employs a passive integrator as the second pole to reduce power consumption, enhance noise performance, and facilitate frequency compensation. The active integrator features a two-stage operational transconductance amplifier (OTA) with a push-pull output, ensuring linearity and reducing the OTA’s gain requirements. Fabricated in standard 0.18-μm CMOS technology, the proposed filter achieves an in-band (IB) input third-order intercept point (IIP3) of +29.9 dBm at 30 MHz and an input-referred IB integrated noise of 163.8 μVRMS, while consuming 5.4 mW for a 50-MHz bandwidth.

A 50 MHz bandwidth (BW) transimpedance ampli-fier (TIA) is designed for 5G Sub-6GHz SAW-less current-mode receivers (RX). It's based on an operational transconductance amplifier (OTA). To tolerate blockers, the TIA must exhibit excellent in-band (IB) and out-of-band (OOB) linearity, which in turn requires OTAs with high BW and gain. Traditional two-stage OTAs struggle to achieve this under low power consumption (PC), so this paper employs a three-stage OTA. A pseudo-differential structure without the tail current source is used to accommodate low supply voltages (Vdd). Differential-mode (DM) stability relies on feedforward (FF) compensation within the OTA and zero compensation in the feedback network. Common mode (CM) is stabilized by five different common mode rejection (CMR) techniques. The circuit is designed and simulated in a 40 nm low power (LP) CMOS technology with a Vdd of 1.2V. The post-layout simulation results show that when IM3 is set to 30 MHz, the TIA's IB and OOB IIP3 reach 31.6 dBm and 50.6 dBm, respectively. The minimum input-referred noise (IRN) is 5.14$\mathbf{nV}/\sqrt{Hz}$. The corresponding FoM value is as high as 186.3 dBJ-1, exceeding all previous designs. The chip consumes 10.4 mW of power and occupies only 0.016mm2.

Envelope tracking (ET) and average power tracking (APT) have been widely used as supply modulators of power amplifiers (PAs). To meet the new challenges brought by the 5G NR standard, the symbol power tracking (SPT) technique is proposed, which is more efficient than ET and more flexible than APT. For the application of subcarrier spacing (SCS) of 15-~60kHz in the frequency range 1 (FR1), this paper proposed a buck-boost SPT supply modulator with a transition time below 1.17-$\mu \text{s}$for 5G NR PA in the smartphone. The combination of three techniques improves the voltage transition speed. The charge-pump-based switching power modulator increases the output voltage higher than the battery voltage and offers a high voltage source for the auxiliary current paths (ACP). The ACP introduces additional currents to charge/discharge the 1-$\mu \text{F}$output capacitor. The end-point-prediction (EPP) scheme lets the compensator convert directly from one steady state to the next. This supply modulator circuit is designed and fabricated using 0.18-$\mu \text{m}$BCD technology. The output voltage range is 1–5-V. The maximum transition speed can be up to 0.37-$\mu \text{s}$/V and 0.15-$\mu \text{s}$/V for up-tracking and down-tracking, respectively.

A wideband LNTA based on cascode inverters is presented, suitable for 5G Sub-6GHz applications. Cascode technique improves the bandwidth, reverse isolation and output impedance. Noise canceling(NC) technology and the new derivative superposition method are adopted to achieve better noise and linearity, respectively. Intrinsic second-order input impedance and off-chip L-type and T-type matching networks are utilized to increase the S11 bandwidth. The use of MOSFETs with different threshold voltages(Vth) simplifies the bias circuit. The first stage of the LNTA is a shunt-shunt feedback LNA, where the feedback resistance Rfaffects the four key performances of gain, bandwidth, noise and linearity. By adjusting the value of Rf, the LNTA can work either in low noise(NF mode) or high linearity(IIP3 mode). The LNTA is designed under the TSMC40nmLP process, and the post-layout simulation shows that the noise figure(NF) can be as low as 1. 52dB under the NF mode. The IIP3 and PldB can reach 10. 58dBm and -1.46dBm respectively under the IIP3 mode. The overall power consumption is only 15. 49mW. The chip core has no inductors and capacitors, making its area only 0.0026mm2.

This paper presents a single-inductor bipolar-input bipolar-output(SIBIBO) DC-DC converter for thermolectric energy harvesting. With an advanced topology, the converter can not only extract energy with bipolar input voltages but also generate bipolar output voltages. To improve the conversion efficiency, the open-circuit voltage maximum power point tracking method is applied in this design. In addition, a precise VCO is proposed to dynamically adjust the switching frequency according to the input voltage. Designed and simulated in an 180nm CMOS process, the harvester achieves a peak conversion efficiency of 90.3% at VTEG=3D200mV and 86.9% at VTEG=3D-190mV.

This paper presents a 4th-order active-RC low-pass filter (LPF) with tunable cut-off frequency (20-50 MHz). To achieve high in-band linearity performance, a three-stage opamp with an operational transconductance amplifier (OTA) output stage is adopted. The first two stages of the opamp only introduce about 45° phase shift using Miller-feedforward hybrid compensation scheme, which guarantees the stability of the filter. The designed opamp can achieve 47 dB gain and 1.4 GHz gain-bandwidth products (GBW) for the filter with 50 MHz cut-off frequency. The post-layout simulation results show that the filter consumes 5.7 mW from 1.1 V supply voltage. The in-band integrated input-referred noise (IRN) is 473 μVrms. The filter achieves 29.8 dBm IIP3 at 30 MHz. Due to the high in-band linearity performance, 153.4 dB · J-1of figure-of-merit is achieved in this design.

This paper presents a Charge-Pump-based SIMO (CPSIMO) buck-boost converter with three operation modes. By modifying the power stage topology of conventional SIMO buck-boost converters, the proposed converter exhibits faster transient response and higher efficiency. Moreover, an average- voltage-based mode selector is introduced to implement the smooth transition between three modes. The proposed converter is designed in TSMC 0.18 μm BCD process with a supply voltage of 2.7V-4.2V and has three outputs of 1.8V, 3.3V and 5V. Simulation results show that the proposed converter achieves a peak efficiency of 94.61% under output power of 2.8W and a load transient response time of 9μs with a 1.5W power step.

A novel 2-D digital predistortion (DPD) algorithm for fully digital Cartesian transmitter is proposed. The nonlinearity of the digital power amplifier in the digital transmitter necessitates DPD for linearization. In order to shorten the setup time of predistortion coefficients in the lookup table (LUT), a profile inversion-based method is adopted. Compared to the traditional adaptive iterative method, the profile inversion method for DPD in this paper shortens the setup time to 15 μs, which is possible for Long Term Evolution (LTE) time division duplex digital transmitter system to execute calibration within every frame. The algorithm is experimentally verified in a fully digital transmitter implemented in 65-nm general process CMOS technology with LUT size of 0.19 mm2, chip size of 2.7 mm2. The digital transmitter has achieved -35- and -32-dBc adjacent channel leakage ratio with 10-MHz LTE and 20-MHz 802.11g WiFi baseband feed in signals, respectively. The DPD improves the linearity of the transmitter by 21 dB for a 2-D constellation signal.

A 65-nm all-digital Class-S transmitter with an entire digital frontend (DFE) and a current-mode Class-D (CMCD) power amplifier (PA) is presented. To realize the high operation rate and performance of the DFE, which includes a 1-bit band-pass ΣA modulator, a mixer, and interpolation filters, approaches, such as time-interleaving algorithm and modified Manchester encoding, are adopted. The main blocks in the DFE are implemented using standard cells with electronic design automation tools for synthesis and place and route. A CMCD PA with an ON-chip transformer is designed and integrated. This Class-S transmitter exhibits a 40-MHz bandwidth at up to a 1.6 GHz output carrier frequency. Measurements with a 1-MHz channel-spacing π/4 quadrature phase shift keying signal show a power control range of -18.66 to -4.65 dBm, and the power consumption of the ΣA modulator core is 7 mW.

This paper presents an energy-efficient reconfigurable 3rd-order continuous-time ΣΔ modulator, which can satisfy multi-band modes for 4G-LTE application. To expand the reconfigurable bandwidth range and optimize the energy efficiency, this work employs a flexible architecture, which can switch between feed-forward and feed-back topologies. At the circuit level, in order to reduce power consumption, flexibility is also introduced into all the core blocks, including amplifiers, multi-bit quantizer and feedback DAC. In addition, multi-bit quantizer utilizes interpolating technique to relax the wide-band amplifier in terms of the low power design. A power-efficient three-stage amplifier with modified positive feedback compensation is used to process high-speed signal and enhance linearity of the modulator. Implemented in 130nm CMOS technology, this work achieves peak SNR of 72.7/66.7/60.4/59.0 dB over 5/10/15/20 MHz BW with 8/14.7/16/21 mW from 1.2V supply, and the respective FOMs are optimized to 227/443/657/773 fJ/conv.

A low-power process-independent programmable transconductance rail-to-rail operational amplifier (OpAmp) is proposed. It employs an improved transconductance feedback loop that senses the transconductance (gmT) accurately and enforces it to be equal to the conductance of a reference resistor. Experimental results in a 0.13- μm standard CMOS technology under a 1-V power supply demonstrate a continuous programmable gmTrange from 87 to 165 μA/V with minimum fluctuation of ±2.4% and programmable deviation less than 4.5% from the reference value. The OpAmp achieves a unity-gain bandwidth of 3.7 MHz with a 95-pF load while only consuming 187 μA of quiescent current. The figure of merit of the proposed OpAmp is 1879 MHz·pF/mA.

This paper presents a ΣΔ DAC with channel filtering for multi-standard wireless transmitters. It can be digitally programmed to satisfy specifications of WCDMA, TD-SCDMA and GSM standards. The measured SFDR are 62.8/60.1/75.5 dB for WCDMA/ TD-SCDMA/ GSM mode, respectively. The ΣΔ DAC manufactured in SMIC 0.13-μm CMOS process occupies a 0.72 mm2die area, while drawing 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage.

A Reconfigurable Analog Processor (RAP), based on the Field-Programmable Analog Array (FPAA) architecture, is designed for mixed-signal processing. The use of coarse-grained, Heterogeneous Configurable Analog Blocks (Hetero-CABs) in the FPAA architecture breaks through the former FPAA design limitations. Both low power design and flexibility are achieved. Mixed-signal processing can be performed by the assistance of an on-chip MCU and Configurable Digital Block (CDB). Relative precision of the analog processing is 99.5%, guaranteed by the minimized use of switches in the FPAA architecture, low-offset design and offset/noise cancelling technique. A PID controller is taken as an application example. RAP is manufactured in SMIC standard 0.18μm CMOS process, the total die area is 11 mm2. The maximum power consumption is 17.6mA with a 3.3V supply voltage, resulting in a 17× improvement in energy-efficiency over current conventional FPAAs.