Three kinds of encoder configurations, which include noise shaping, predictive and their combination forms, are investigated from LSI implementation points of view. A first order predictive encoder with first order noise shaping is chosen. A novel circuit configuration for the selected structure is proposed, which consists of a digital predictor with a capacitor array D-to-A converter, an operational amplifier and a comparator. The configuration can greatly decrease step unbalance effect, settling time and output voltage swing requirements for the operational amplifier, and the number of analog components. These features are essential in fine pattern LSI implementation. Capacitor fabrication error effects on the signal-to-noise ratio are numerically analyzed. A simplified decimation filter realization, which needs no high speed multiplier, is introduced.

A discretely variable slope delta modulation (DVSD) codec is described, which is suitable for integrated circuit realization. The step size is varied by a pulse number modulation method that does not require a precision digital-to-analog conversion circuit. An adaptation algorithm is discussed, taking into consideration the effect of transmission errors. The quantizer and integrator portion has been fabricated on a monolithic chip using MOS technology. Results obtained from an experimental 32 kbit/s codec demonstrate its excellent performance.