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Wieland Fischer

dblp:06/1025 · DBLP profile ↗
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9ranked-venue papers
8as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 8 · 7 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
3 papers
Hardware security and side channels · 82% Cryptographic primitives and cryptanalysis · 18%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 60% Hardware accelerators and domain-specific architectures · 40%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › side-channel countermeasures › masking
glitch-resistant masking
0.112005
Masking at Gate Level in the Presence of Glitches · CHES 2005
Hardware security and side channels › side-channel countermeasures
masking
0.112005
Masking at Gate Level in the Presence of Glitches · CHES 2005
Hardware security and side channels › hardware attacks
side-channel and fault attacks
0.112005
Masking at Gate Level in the Presence of Glitches · CHES 2005
Cryptographic primitives and cryptanalysis
public-key cryptography
0.022002
Increasing the Bitlength of a Crypto-Coprocessor · CHES 2002
Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures · CHES 2002
Hardware security and side channels
fault attacks
0.012002
Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures · CHES 2002
Hardware security and side channels › fault attacks
RSA-CRT fault attacks
0.012002
Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures · CHES 2002
Hardware security and side channels › trusted execution environments
secure coprocessor
0.012002
Increasing the Bitlength of a Crypto-Coprocessor · CHES 2002
Integrated circuit design
digital circuit design
0.012005
Masking at Gate Level in the Presence of Glitches · CHES 2005
Cryptographic primitives and cryptanalysis › cryptographic implementation
CRT-RSA
0.012002
Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures · CHES 2002
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.012002
Increasing the Bitlength of a Crypto-Coprocessor · CHES 2002

Methods — techniques the papers use, named apart from their topics

masking · 0.1glitch analysis · 0.1modular arithmetic · 0.1coprocessor design · 0.1fault injection · 0.0countermeasures · 0.0
YearPublicationVenuePosition
2012 Differential Fault Analysis on Grøstl
abstract
This paper presents a DFA on Grøstl-256, a hash algorithm that imitates the main structures of AES. Although our attack is inspired by the classical fault attacks on AES these could not be adapted directly. The attack is able to completely recover the whole input message using a one-bit and a random-byte fault model. It needs 16 errors to invert the output transformation Ωnand on average 280 errors for each compression step. When Grøstl is used in a keyed hash function like HMAC, this attack is able to retrieve the secret key from about 300 faulty outputs in less than three minutes.
Wieland Fischer, Christian A. Gorke
FDTC1
2008 Aspects of the Development of Secure and Fault-Resistant Hardware
abstract
Designing "secure hardware" like a chip card controller, is a challenging task for hardware manufacturers: More and more attacks that are also more and more sophisticated generate a need for more and more countermeasures. Developers of these devices have to live with certain additional constraints and this does not make their life easier. The difficulties that the designer of such a system is confronted with, are pointed out. This might give the scientific community some impression of the problems that would be interesting to be solved.
Wieland Fischer
FDTC1
2007 Differential Power Analysis of Stream Ciphers
Wieland Fischer, Berndt M. Gammel, O. Kniffler, Joachim Velten
CT-RSA1
2005 Masking at Gate Level in the Presence of Glitches
Wieland Fischer, Berndt M. Gammel
CHES1
2004 High-Speed Modular Multiplication
Wieland Fischer, Jean-Pierre Seifert
CT-RSA1
2003 Unfolded Modular Multiplication
Wieland Fischer, Jean-Pierre Seifert
ISAAC1
2002 Note on Fast Computation of Secret RSA Exponents
Wieland Fischer, Jean-Pierre Seifert
ACISP1
2002 Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures
Christian Aumüller, Peter Bier, Wieland Fischer, Peter Hofreiter, Jean-Pierre Seifert
CHES3
2002 Increasing the Bitlength of a Crypto-Coprocessor
Wieland Fischer, Jean-Pierre Seifert
CHES1