As one of the most promising approaches for the automatic generation of VLSI chips, the concept of "silicon compilers" was presented. A silicon compiler is a software system which accepts the behavioral or functional description of the chip and directly translates it to the layout patterns of the VLSI masks. In order to realize a design automation aid for full-custom VLSI chips for nonprofessional chip designers such as programmers, we have selected asynchronous architecture as the target model of the compiler and have been developing a silicon compiler system. A VLSI chip based on this architecture model consists of asynchronous modules which hold the control information internally. The behavior of the chip is controlled only by local communication among these modules. The silicon compiler system accepts the purely functional specifications of the chip, written by the hardware specification language ISPC, and directly translates it to the layout patterns in the form of CIF codes. By selecting an effective architecture model, it is possible to realize the silicon compiler system through simple translation programs which analyze the functional description of the chip and extract from it the configuration of components and the control information and through a library of the asynchronous modules which are generally defined with suitable parameters.

In order to realise dedicated functions that have no special parallel algorithms for efficient full custom VLSI implementation, we propose an asynchronous architecture that consists of several asynchronous functional modules and controls the chip by the local communication among these functional modules. As this architecture is very suitable for mapping from the behavioral specification described by the software onto silicon, it is very useful as a target architecture for silicon compilers. This paper describes the concept and the VLSI implementation of the asynchronous architecture. An evaluation of the size and the execution speed of chips based on this architecture model is also described.

In this paper we discuss about another approch: Compiler Chip, which is a VLSI implementation of a compiler. Constructing a compiler by a few VLSI chip, the computer manufacturer can deliver compilers by sets of VLSI chips, and these chips are installed in a intelligent terminal in order to remove the compilation from the tasks which are processed in the mainframe.