The quality of a communication link is commonly indicated by signal to noise/interference ratio and affected by noise and interference variance. To ensure a power efficient adaptive OFDM system's performance, the system needs to be tested against various channel conditions. Conventional algorithms and experiments assume that the noise and interference density stays constant over the OFDM frequency band but in reality the communication link often populated with both white noise and interference that results an uneven impact on OFDM spectrum. To create such channel condition, an up-conversion is commonly used. However, due to the non-linearity of the mixer, the up-converted interference is always distorted. The proposed method uses a modified higher-than-Nyquist-rate RF signal generation algorithm to minimize the distortion of generated interference within a pre-defined output bandwidth. Both concept validation and experimental measurement have been conducted to prove the effect of proposed method.

Modern radio front ends are required to operate over diverse channel conditions requiring the incorporation of significant performance overheads into their design. This results in significantly higher power consumption over most of the operational period since the worst case channels are not statistically prevalent. Adaptive systems solve this problem by adapting the performance and power consumption depending on channel conditions. In this paper, it is demonstrated that depending upon the throughput requirements of the system multiple low-power adaptation modes can be designed. These modes ensure either highest throughput operation or lowest energy-per-bit operation. The operation of these modes is demonstrated in simulation using multiple-input-multiple-output (MIMO) receiver and transmitter front ends. Subsequently, the concepts are demonstrated in hardware for both MIMO and single-input-single-output front ends.

Prior research has established that dynamically trading-off the performance of the RF front-end for reduced power consumption across changing channel conditions, using a feedback control system that modulates circuit and algorithmic level "tuning knobs" in real-time, leads to significant power savings. It is also known that the optimal power control strategy depends on the process conditions corresponding to the RF devices concerned. This complicates the problem of designing the feedback control system that guarantees the best control strategy for minimizing power consumption across all channel conditions and process corners. Since this problem is largely intractable due to the complexity of simulation across all channel conditions and process corners, we propose a self-learning strategy for adaptive MIMO-RF systems. In this approach, RF devices learn their own performance vs. power consumption vs. tuning knob relationships "on-the-fly" and formulate the optimum reconfiguration strategy using neural-network based learning techniques during real-time operation. The methodology is demonstrated for a MIMO-RF receiver front-end and is supported by hardware validation leading to 2.5X power savings in minimal learning time.

This paper proposes a self-tuning architecture for buck converters based on a modified alternative “safe” testing approach. It avoids voltage spikes caused by conventional full load testing and provides measurements with strong statistical correlation with the DUT's specifications. The measurements are sampled by a 5-bit ADC and analyzed by on-chip resources for evaluating the DUT specifications and predicting the corresponding values of buck converter tuning knobs to compensate for process variations when standard performances are not met. Thus, the proposed methodology enables self-test and self-tuning of buck converters during production test without the risk of DUT damage during standard production test. The causes of voltage spikes during conventional full load test are discussed both analytically and numerically and the working mechanism of an alternative test procedure is developed. This proposed technique is demonstrated through both simulation and hardware validation experiments.

This paper presents a novel alternative “safe” test method for line and load regulation specifications of hysteretic controlled switching power converters. These specifications have not been tested in production before because the conventional measurement techniques lead to huge voltage spikes during switching transients. Those voltage spikes are caused by energy accumulation from parasitic inductances of ATE interface board to input capacitance of the device under test (DUT) and can damage DUT's internal circuitries. The proposed alternative test approach offers a “safe” manufacturing test of load/line regulation specifications of hysteretic controlled switching power converters through a carefully altered feedback circuit and a current-limited load. Through injecting the altered feedback circuit with a carefully crafted stimulus, the load and line regulation specifications of DUT are accurately predicted. This test approach is facilitated by the use of a DAC for stimulus generation and ADC for DUT response capturing. Both simulated data and hardware measurements are used to demonstrate the viability of the proposed ”safe”testing method.

Phase-locked loops are used to synthesize frequency sources for RF conversion and IO clocks for data synchronization, and serve as core building blocks for communication systems. Consequently, testing of PLL loop performance is critical for guaranteeing the reliability of the underlying communication systems. In this paper, a testing method based on loop triggering and use of low-cost built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensors are designed in such a way that the sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learners are "trained" to predict the required PLL parameters from the observed sensor response. A PLL is designed and simulated in closed loop over PVT corners in order to validate the testing mechanism. Parameters including charge pump current, VCO gain, bandwidth, phase margin, and locking time are predicted accurately and concurrently over these PVT corners to prove the viability of the proposed test method.

This paper proposes a novel test method for the line and load regulation specifications of switched mode power converters (SMPCs) using alternative safe measurements. These specifications are not tested for many power converters because they cause voltage spikes under full load conditions on the tester that can damage the converter circuitry. To prevent damage to the DUT during manufacturing test, we propose a modification of the power converter load during test application. Optimized low cost tests are applied to the converter under low load current conditions, allowing accurate prediction of the closed-loop load and line regulation specifications (that require high load current) from the modified test procedure without the possibility of any damage to the DUT. The test approach is facilitated by the use of two sensors that allow the line and load regulation specifications of the converter to be predicted accurately from the proposed alternative test measurements. Simulation data and measurements from a hardware prototype are used to demonstrate the viability of the proposed safe testing approach.

In this paper, a higher than Nyquist RF test waveform synthesizer with digital phase noise injection is proposed. The proposed system uses time-interleaved digital-to-analog converters (DACs) and associated digital signal processing algorithms to enhance the spectral image of the synthesized waveform in the high-order Nyquist zones by increasing the effective sampling rate and eliminating unwanted signals inside the bandwidth of interest. The generated spectral images are used as the primary output of the proposed system. The waveform synthesizer is capable of digitally controlling the phase noise characteristics of the output signal in the high-order Nyquist zones. In addition, it utilizes relatively low-cost off-the-shelf integrated circuits (ICs) for multi-GHz signal generation. In hardware validation, dual DACs operating at 2.5Gb/s (effective Nyquist rate of 5 Gb/s) are used to generate a signal centered at 3.2GHz (corresponding to a Nyquist rate of 6.4 GHz). In addition, controlled phase noise generation is demonstrated.

In this paper, we propose a wideband signal reconstruction scheme for testing high-speed pseudo random bit sequences (PRBSs) in the presence of jitter noise using incoherent sampling. The proposed approach exploits synchronous multirate sampling (SMRS) hardware and multicoset back-end signal processing algorithms. The SMRS hardware consists of multiple analog-to-digital converters (ADCs) whose sampling frequencies are synchronized with a common frequency reference and can be individually configured. The optimal sampling frequency of each ADC is chosen based on the input signal information and sampling hardware specifications. As compared to other sampling hardware used for multicoset signal reconstruction, the proposed approach uses less number of ADCs and does not require accurate sampling clock phase adjustment. In the digital signal reconstruction, the input waveform is reconstructed by the multicoset signal processing algorithms and the phase noise of each tone of the PRBS test signal is measured.

In this paper, we propose a new test response acquisition technique for high-speed devices-based on dual-frequency incoherent sub-sampling and sparse signal reconstruction. The proposed technique enables reconstruction of spectrally sparse wideband signals such as multi-tone signals and short pseudo-random bit sequences (PRBS) with enhanced time/frequency resolution as opposed to current methods. The sampling hardware utilizes dual analog-to-digital converters (ADCs) and dedicated sampling frequency synthesizers with a common frequency reference. As compared to other compressive sampling architectures [1], the proposed hardware architecture is easy to implement at low cost since it does not require accurate sampling clock phase adjustment or random timing generation. For digital signal reconstruction, the proposed technique requires less number of waveform samples than conventional equivalent-time sampling techniques. In addition, the use of an resolution-enhanced discrete Fourier transform (DFT) frame and basis pursuit algorithms minimizes spectral leakage of incoherently sub-sampled signals. This co-design of sampling hardware and signal reconstruction algorithms enables testing of spectrally sparse wideband signals with enhanced time/frequency resolution.