This paper presents a fully integrated 2.9-Gb/s spread-spectrum clocking (SSC) wireline transceiver designed for high-speed chip-to-chip links. The architecture combines a digitally controlled phase interpolator (DCPI) in the transmitter and an analog-controlled phase interpolator (ACPI) in the receiver, leveraging the programmability of digital control and the low-jitter performance of analog control. A 2.9-GHz four-phase phase-locked loop (PLL) provides reference clocks for both SSC generation and clock/data recovery (CDR). In the transmitter, the DCPI synthesizes SSC-modulated clocks and drives the data path, supporting downward triangular modulation depths up to 3 % at a 44.25-kHz modulation frequency. In the receiver, a quarter-rate SSC-compatible CDR with hybrid PI control recovers the SSC clock and data with fine phase alignment and low jitter. Fabricated in a 90-nm CMOS process and occupying a 1.2 mm$\times 1.2$mm die, the proposed transceiver achieves robust electromagnetic-interference (EMI) suppression, with the SSC generator providing up to 26.78 dB EMI attenuation.

Without any dummy element for phase compensation, a clock-deskewing circuit (CDC) using a master-slave delay-locked loop (MSDLL) configuration is presented to synchronize the clocks for cascaded core-to-core links. The dual-locking CDC provides mismatch-insensitive compensation of interconnected wires, input/outputs (IOs), and clock buffers. The MSDLL incorporates the digital-selection folded coarse-fine voltage-controlled delay line (FCF-VCDL) to provide a wide range operations. The proposed FCF-VCDL scheme is constructed from the combination of positive and negative gains of different VCDLs. In addition, a power-controlled regime is employed in the FCF-VCDL to adaptively lower the power dissipation. Implemented with 0.18- μm CMOS, the CDC can provide 20 MHz to 2 GHz with the help of FCF-VCDLs. The 2-GHz clock jitter is 6.78 ps (pk-pk), and the total power dissipation is 20 mW under a 1.8-V supply.

A 6-bit flash analog-to-digital converter (ADC) using reference-voltage-interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs the successive approximation algorithm and the minimized residue algorithm to determine precise calibration levels. Implemented by a 90-nm CMOS process, the proposed ADC can achieve a signal-to-noise-and-distortion ratio of 36 dB for a low input frequency and 33.5 dB for a Nyquist-rate input frequency at a 2-GS/s sampling rate. The peaks of integral and differential nonlinearities after calibration are 0.36 and 0.42 least significant bit, respectively. The power consumption is 25 mW at 2 GS/s from a 1.2 V supply. The core area is 0.32 mm × 0.62 mm, and the figure of merit is 0.34 pJ/conversion step.

In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) circuit using a 4× oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed circuit can recover the burstmode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is embedded in the chip. Implemented with a 0.18-μm CMOS technology, experiment shows that the acquisition time can be accomplished in the time of 31 bits. Incoming 2.5-Gb/s input data of 231-1 pseudorandom binary sequence, the retimed data has a root-mean-square jitter of 8.557 ps and a peak-to-peak jitter of 32.0 ps, and the measured bit error rate is less than 10-10. The area of the whole chip is 1.4 × 1.4 mm2, where the BMCDR circuit core occupies 0.81 × 0.325 mm2. The total power consumption is 130 mW from a 1.8 V supply voltage.

A 2-GS/s 6-bit flash analog-to-digital converter (ADC) in 90nm CMOS is presented. Using the reference-voltage-interpolated calibration reduces bandwidth requirements on the comparator to enable high sampling rates with low power consumption. The ADC consumes 28 mW and occupies 0.35 mm2. The proposed calibrated technique improves ENOB from 3.0 to 5.1 with an input sinusoid at Nyquist frequency.

A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply.

The paper describes an embedded circuit for the single shot jitter measurement of the clock signal. Based on a jitter amplified technique with a pulse removing mechanism, the pico-second level resolution is achieved in the wide frequency range. In addition, a gain-locked loop calibration scheme is proposed to keep the amplification ratio constant under PVT variations. Fabricated by 0.13-um CMOS process, the tested circuit can achieve a resolution of 2 ps root mean square (rms) jitter at an input range from few tens of megahertz to 1.6 GHz.

A fractional-N frequency synthesizer for IEEE 802.11a/b/g standard with the design focused on voltage controlled oscillator (VCO) is proposed in this paper. Unlike the traditional approach of tuning VCO oscillation frequencies by capacitive varactors, the proposed VCO with a voltage-controlled inductor, which is made by an integrated transformer technology, is adopted. A digital delta-sigma modulator realized with FPGA verification is employed for fractional-N purpose to meet IEEE 802.11a/b/g channels. The frequency synthesizer is simulated in 0.18-/spl mu/m CMOS process with a loop-bandwidth of 300 KHz for a 32-MHz reference and the power dissipation is about 40 mW from a 1.8-V supply.

In this paper, a burst-mode clock and data recovery (CDR) circuit using a 1/4-rate clock technique is realized for optical communication system. The CDR circuit contains a phase detector and a muxed-oscillator to control the phase of the clocks. In-lock operation is accomplished on the first data transition, and after the first data the clocks are in phase for all data until the data transition is over. The CDR circuit is implemented with 0.18-/spl mu/m CMOS technology. The experimental results show that the proposed CDR circuit recover the incoming 1.8-Gb/s data.

A 0.35-/spl mu/m CMOS instrumentation amplifier with automatic gain control (AGC) system for the sensor interfaces is presented in this paper. The circuitry employs a chopper stabilization technique to significantly reduce the low-frequency noise and DC offset. The AGC is used in the system where the amplitude of an incoming signal can vary over a wide dynamic range. The AGC circuit provides relatively constant output amplitude in spite of the sensitivity of the sensor due to the parameter variations. Furthermore, the whole system has been kept fully differential operation in order to get higher immunity to environmental noise of supply voltages, clock feedthrough, charge injection, even harmonic distortion, etc. It features a gain of 53/spl plusmn/17 dB with 25-kHz bandwidth. The equivalent input noise is about 1.13 /spl mu/V/sub pp/ at 98.2-kHz chopper frequency.