Abstract Recent advances on sensor network technology provide the infrastructure to create intelligent environments on physical places. One of the main issues of sensor networks is the large amount of data they generate. Therefore, it is necessary to have good data analysis techniques with the aim of learning and discovering what is happening on the monitored environment. The problem becomes even more challenging if this process is performed following an unsupervised way (without having any a priori information) and applied over a long‐term timeline with many sensors. In this work, topic models are employed to learn the latent structure and dynamics of sensor network data. Experimental results using two realistic datasets, having over 50 weeks of data, have shown the ability to find routines of activity over sensor network data in office environments.

Looking forward to the next generation of mobile streaming computing, the demanded energy efficiency of end-user terminals will become ever stringent. The Xetal-Pro processor, which is the latest member of the Xetal low-power single-instruction multiple data (SIMD) processor family from Philips, is presented in this paper. The predecessor of Xetal-Pro, known as Xetal-II, already ranks as one of the most computational-efficient [in terms of giga operations per second (GOPS)/Watt] processors available today, however, it cannot yet achieve the demanded energy efficiency (less than 1 pJ per operation). Unlike Xetal-II, Xetal-Pro supports ultrawide supply voltage (Vdd) scaling from the nominal supply to the subthreshold region. Although aggressiveVddscaling causes severe throughput degradation, this can be partly compensated for by the massive parallelism in the Xetal family. Xetal-II includes a large on-chip frame memory (FM), which cannot be scaled well to an ultralowVddhence creating a big obstacle to increase energy efficiency. Therefore, we investigate both different FM realizations and memory organization alternatives. A hybrid memory system (HMS), which reduces the non-local memory traffic and enables furtherVddscaling, is proposed. For design space exploration of the right number of the scratchpad memory (SM) entries, the corresponding data locality analysis is provided, too. Moreover, some unique circuit implementation issues of Xetal-Pro such as the customized level-shifter are also discussed. Compared to Xetal-II operating at the nominal voltage, Xetal-Pro provides up to two times energy efficiency improvement even withoutVddscaling (essentially a consequence of data localization in the SM) when delivering the same amount of ultrahigh throughput. WithVddscaling into the sub/near threshold region, Xetal-Pro could gain more than ten times energy reduction while still delivering a high throughput of 0.69 GOPS (counting multiply and add operations only). The new insight of Xetal-Pro sheds light on the direction of future ultralow-energy SIMD processors.

This paper presents Xetal-Pro SIMD processor, which is based on Xetal-II, one of the most computational-efficient (in terms of GOPS/Watt) processors available today. Xetal-Pro supports ultra wide V DD scaling from nominal supply to the sub-threshold region. Although aggressive V DD scaling causes severe throughput degradation, this can be compensated by the nature of massive parallelism in the Xetal family. The predecessor of Xetal-Pro, Xetal-II, includes a large on-chip frame memory (FM), which cannot operate reliably at ultra low voltage. Therefore we investigate both different FM realizations and memory organization alternatives. We propose a hybrid memory architecture which reduces the non-local memory traffic and enables further V DD scaling. Compared to Xetal-II operating at nominal voltage, we could gain more than 10× energy reduction while still delivering a sufficiently high throughput of 0.69 GOPS (counting multiply and add operations only). This work gives a new insight to the design of ultra-low energy SIMD processors, which are suitable for portable streaming applications.

Digital vision processing becomes more portable and vision sensors steadily drop in price. Together this leads to vision innovations for 3-D and higher tasks ranging from the stand-alone intelligent camera to the smart collaboration of casual sensors. Local intelligent operations will bring out features, on which information can be exchanged globally. This fuses by means of a modular neural network. The paper discusses methods for overall distributed systems training that differ in the handling of communication bandwidth issues. It illustrates how artifacts due to abnormal emergent behavior can be avoided.

While providing a variety of intriguing application opportunities, a vision sensor network poses three key challenges. High computation capacity is required for early vision functions to enable real-time performance. Wireless links limit image transmission in the network due to both bandwidth and energy concerns. Last but not least, there is a lack of established vision-based fusion mechanisms when a network of cameras is available. In this paper a distributed vision processing implementation of human pose interpretation on a wireless smart camera network is presented. The motivation for employing distributed processing is to both achieve real-time vision and provide scalability for developing more complex vision algorithms. The distributed processing operation includes two levels. One is that each smart camera processes its local vision data, achieving spatial parallelism. The other is that different functionalities of the whole line of vision processing are assigned to early vision and object-level processors, achieving functional parallelism based on the processor capabilities. Aiming for low power consumption and high image processing performance, the wireless smart camera is based on an SIMD (single-instruction multiple-data) video analysis processor, an 8051 micro-controller as the local host, and wireless communication through the IEEE 802.15.4 standard. The vision algorithm implements 3D human pose reconstruction. From the live image data from the sensor the smart camera acquires critical joints of the subject in the scene through local processing. The results obtained by multiple smart cameras are then transmitted through the wireless channel to a central PC where the 3D pose is recovered and demonstrated in a virtual reality gaming application. The system operates in real time with a 30 frames/sec rate.

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding–decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called Dual Rail, is then proposed. It is shown that Dual Rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13- $\mu{\hbox{m}}$ CMOS technology.

This paper describes a new smart camera mote with a high performance SIMD (single-instruction multiple-data) processor. Previous versions of our camera mote were equipped with IC3D, a line-based processor. The mote described in this paper is equipped with Xetal-II, a processor designed for frame-based real-time video analysis. The processor uses 320 processing elements in parallel to achieve performance figures of more than 100 GOPS with a power consumption of 600 mWatt at peak performance. The IC has a 10 Mbit internal memory cache to store and work on 4 VGA frames. The internal bandwidth to this memory is more than 1.5 Tbit/s allowing multiple passes over the images within frametime. Augmented with hardware tools for object processing, the new mote opens the door for embedded active vision applications and other iterative techniques such as watershedding and distance transforms in collaborative camera networks.

A network of (wireless smart) cameras can analyse the scene from different views. Wireless smart cameras challenge the hardware for low-power consumption and high imaging performance. In this paper we introduce a wireless smart camera based on an SIMD video-analysis processor and an 8051 microcontroller as a local host. Wireless communication is through the IEEE 802.15.4 standard. The camera constructed in this paper is to enable application research into distributed smart camera systems.

There is a rapidly growing demand for using smart cameras for various biometric applications in surveillance. Although having a small form-factor, most of these applications demand huge processing performance for real-time processing. Face recognition is one of those applications. In this paper we show that we can run face recognition in real-time by implementing the algorithm on an architecture which combines a parallel pixel processor: with a digital signal processor. The algorithm consists of a cascade of filters for detection, registration and normalization and an RBF neural network with temporal filtering. Everything fits within a digital camera, the size of a normal surveillance camera.

Fault tolerant design is a technique emerging in Integrated Circuits (IC's) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects (the Hard Errors). Currently, yield engineers focus on perfecting the manufacturing process and designers spend their effort in minimizing the area to increase the yield. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques) leads under certain conditions to a better yield (more working dies from a wafer) and lower production cost. This is counter-intuitive for many design and yield engineers. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular design are presented as function of IC area, fault tolerant overhead and defect density.

On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay variations and transient faults. Error correcting codes can be employed in order to provide signal transmission with the necessary data integrity. We compared Dual Rail encoding versus Hamming with respect to power consumption of the bus wires themselves (passive capacity model) [Rossi et al., 2002]. In this paper we analyze the contribution of the active elements of both coding schemes. We first present a detailed analysis of the power consumption of an encoded bus, taking into account the bus wires (with mutual capacitances, drivers, repeaters and receivers), as well as the encoding/decoding circuitry. Then we compare the two considered coding technique with respect to the power consumption, and we show how different tradeoffs can be achieved. Our analysis is based on a realistic bus structure, implemented in a 0.13/spl mu/m CMOS technology.

This article describes a 30 frames/second VGA format image sensor made in a standard CMOS process with an embedded massively parallel processor. The processor is fully programmable and therefore the sensor IC itself is able to run a variety of algorithms with data and processing in close vicinity of the sensor. Because of the parallel architecture comprising processor array and parallel memory accesses, high computational performances of up to 5 GOPS at 16 MHz are achieved. This high performance allowed us to implement skin tone detection on the camera itself as part of a larger system for face recognition, releasing the host computer of cumbersome pixel processing tasks and minimizing the data transfer between camera and computer.

We present a new solution for storing a variable number of images in a fixed storage space at the highest overall quality. Initially, when only a few images are stored, they are stored losslessly (or near-losslessly). When more images have to be added, the storage space occupied by the previously stored images is adjusted optimally, in the rate-distortion sense, to fit in each new image. Thus, a variable amount of space is allocated to each image, depending on its complexity. The implementation is based on bit-rate scalable image compression methods, which enables the data for each new image to simply overwrite part of the data of previously stored images. Thus, the method operates without any decoding and re-encoding of image data on the storage medium. To illustrate the concept, we present the results of our experiments for a digital image camera application.

We have developed a scalable image compression scheme with a good performance-complexity trade-off. Like JPEG, it is based on the 8/spl times/8 block discrete cosine transform (DCT), but it uses no additional quantization or entropy coding (such as Huffman or arithmetic coding). Bit-rate or quality scalability is enabled by encoding the DCT coefficients bit plane by bit plane, starting at the most significant plane. The individual bit planes are efficiently encoded using simple rectangular zones. Our method offers about the same compression performance as JPEG, but at a significant lower complexity and with the additional feature of scaling the bit rate by simply truncating the generated bit string.

A transpose switch matrix memory (TSMM) is proposed to enable a highly parallel single-chip CMOS sensor/image processor, Xetal, developed at Philips to perform JPEG compression at video rate (30 frames per second, fps) at an image dimension of 640/spl times/480 pixels. The integrated solution consists of 320 processing elements and 80 TSMMs, operates at 16 MHz clock rate and 3.3 V supply voltage, and is designed for fabrication at 0.25 micron technology. The processing system can sustain a maximum throughput of 5.12 billion operations per second consuming an estimated 120 mW providing a processing power efficiency of 7 BOPS/Watt. The Xetal architecture is capable of performing pixel level image processing such as fixed pattern noise (FPN) correction, defective pixel concealment, Bayer pattern filtering, RGB-YUV conversion, auto white balancing, and auto exposure control. The TSMM expands support to block level operations including chrominance subsampling, separable 8/spl times/8 recursive DCT, and ZZ scan required for JPEG.

We have developed a scalable image compression scheme with a good performance-complexity trade-off. Like JPEG, it is based on the 8/spl times/8 block discrete cosine transform (DCT), but it uses no additional quantization or entropy coding (such as Huffman or arithmetic coding). Bit-rate or quality scalability is enabled by encoding the DCT coefficients bit plane by bit plane, starting at the most significant plane. The individual bit planes are efficiently encoded using simple rectangular zones. Our method offers about the same compression performance as JPEG, but at a lower complexity and with the additional feature of scaling the bit rate by simply truncating the generated bit string.

Original video signals are often corrupted by a certain amount of noise originating from the camera electronics. As a result of the gamma correction in cameras, the observed noise is signal dependent. We present a spatio-temporal order-statistic (OS) noise filter that takes into account the gamma correction in the camera. The calculation of the filter coefficients requires higher-order order-statistics (HOOS) of the noise process. We make use of a range test (RT) to determine locally from which neighboring signal values an estimate should be formed. The noise filter that we arrive at is adaptive and computationally efficient.

In this paper, a thorough review is presented of noise reduction filters for digital image sequences. Detailed descriptions of several spatiotemporal and temporal noise reduction algorithms are provided. To aid in comparing between these different algorithms, we classify them based on their support (i.e., 3-D or 1-D filter) and whether or not motion compensation is employed. Several algorithms from each of the four categories are implemented and tested on real sequences degraded to various signal-to-noise ratios. These experimental results are discussed and analyzed to determine the overall advantages and disadvantages of the four general classifications, as well as, the individual filters.>

In this paper, a new spatio-temporal filtering method for removing noise from image sequences is proposed. This method combines the use of motion compensation and signal decomposition to account for the effects of object motion. Because of object motion, image sequences are temporally nonstationary, which requires the use of adaptive filters. By motion compensating the sequence prior to filtering, nonstationarities, i.e., parts of the signal that are momentarily not stationary, can be reduced significantly. However, since not all nonstationarities can be accounted for by motion, a motion-compensated signal still contains nonstationarities. An adaptive algorithm based on order statistics is described that decomposes the motion-compensated signal into a noise-free nonstationary part and a noisy stationary part. An RLS filter is then used to filter the noise from the stationary signal. Our new method is experimentally compared with various noise filtering approaches from literature.

Even original video sequences are often corrupted by a certain amount of noise. As a result of the gamma-correction in cameras, the observation noise is signal-dependent. We present a spatio-temporal order statistic (OS) noise-filter that takes into account the gamma-correction in the camera. This filter uses higher-order order statistics (HOOS). We make use of a range-test (RT) to determine on which signal values an estimate should be based. The noise-filter obtained in this way is adaptive and computationally efficient.>