This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store & forward (S&F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.

This paper presents a network emulator for rapid prototyping of SpaceWire Intellectual Property cores. SpaceWire is a fault-tolerant high-throughput standard widely used in space and avionic applications. Thanks to its inherent properties, SpaceWire can be effectively adopted for addressing dependability and bandwidth requirements of forthcoming active safety automotive applications. The proposed platform considers both anti-fuse and SRAM FPGA devices. A four-layer software stack ensures full control of prototype features, batch testing and ease of use.

Clock distribution is an important issue when designing multi processor systems-on-chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a multi processor tiled architecture based on a network-on-chip communication backbone on a CMOS 65 nm technology.

The amount of electronic systems introduced in vehicles is continuously increasing: X-by-wire, complex electronic control systems and above all future applications such as automotive vision and safety warnings require in-car reliable communication backbones with the capability to handle large amount of data at high speeds. To cope with this issue and driven by the experience of aerospace systems, the SpaceWire standard, recently proposed by the European space agency (ESA), can be introduced in the automotive field. The SpaceWire is a serial data link standard which provides safety and redundancy and guarantees to handle data-rates up to hundreds of Mbps. This paper presents the design of configurable SpaceWire router and interface hardware macrocells, the first in state of the art compliant with the newest standard extensions, Protocol Identification (PID) and remote memory access protocol (RMAP). The macrocells have been integrated and tested on antifuse technology in the framework of an ESA project. The achieved performances of a router with 8 links, 130 Mbps data-rate, 1.5 W power cost, meet the requirements of future automotive electronic systems. The proposed networking solution simplifies the connectivity, reducing also the relevant volume and mass budgets, provides network safety and redundancy and guarantees to handle very high bandwidth data flows not covered by current standards as CAN or FlexRay

In this paper, a digital RFI (radio frequency interference) canceller for DMT (discrete multitone modulation)-based VDSL (very high-speed digital subscriber line) systems is presented. The adopted algorithm is optimized in terms of performance vs. complexity and size of the involved memories. High level, maximum precision system simulations showed the effectiveness of the cancellation scheme, considering VDSL performance parameters such as bit rate and efficiency in counteracting performance degradation due to RFI. The canceller has been implemented as a hardware macro-cell: the design space already explored at algorithm level to meet a good complexity/performance trade-off, has been deeply investigated during the bit true analysis to fix the finite numeric representation, the micro-architecture definition and the final technology mapping. Results of logic synthesis on a standard cells 0.18 /spl mu/m CMOS technology are reported, in terms of area and energy consumption.