The thermionic limit of conventional MOSFET hinders steep slope switching, requiring at least 60 mV gate voltage to modulate the current at room temperature. In this work, we adopted a multiscale simulation approach to investigate sub 10 nm gate length cold source field effect transistors (CS FET) based on edge-oxidized armchair phosphorene nanoribbons (APNR-O). We showed that the presence of narrow DOS in APNR-O could filter out the high energy electrons, thus bringing the subthreshold swing (SS) down to a minimum value of 40 mV/decade and an average value of 58 mV/decade for a four-decade increase in drain current (IDS). An on current (ION) of 1418.5 µA/µm and ION/IOffratio of 2.1 × 106was achieved by the proposed device. Low switching energy (PDP) and fast switching speed (τ) of ∼0.15 fJ/µm and ∼0.35 ps, respectively, were predicted in this work. These results indicate that the APNR-O-based FET can simultaneously fulfill the requirements of the International Roadmap for Devices and Systems (IRDS) both for high-performance (HP) and low-power (LP) devices in 2028. Hence, the APNR-O can be a good channel material for more than Moore devices.

Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6 T SRAM cells. To overcome this limitation, 7 T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6 T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6 T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7 T TFET SRAM cell. We achieve a leakage reduction improvement of 700 X and 1600 X over traditional CMOS SRAM designs at VDDof 0.3 V and 0.5 V respectively which makes it suitable for use at ultra-low power applications.

The occupancy of caches has tended to be dominated by the logic bit value `0' approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value `0' occupancy ratios even further. We investigate how Negative Bias Temperature Instability (NBTI) affects different power saving cache strategies employing symmetric and asymmetric 6- transistor (6T) and 8T Static Random Access Memory (SRAM) cells. We notice that greater than 38% to 66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM cells based caches. We also study the process variations effect along with NBTI for 32nm and 45nm technology node. It is observed that the rate of recovery in asymmetric SRAM cells based caches is slightly higher than the symmetric and 8T SRAM cells based caches.

This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-VDDand low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, 65 nm CMOS technology node to evaluate and compare different performance parameters. The active power dissipation in the proposed 6T design is 28% and 25% less, compared to standard 6T and 8T SRAM modules respectively.

In this paper, we present a systematic method for the designing fault tolerant reversible arithmetic circuits for finite field or Galois fields of the form GF(2m). To tackle the problem of errors in computation, we propose error detection and correction using multiple parity prediction technique based on low density parity check (LDPC) code. For error detection and correction, we need additional garbage outputs. Our technique, when compared with traditional fault tolerant approach gives better implementation cost.

Motivated by the problems associated with soft errors in digital circuits and fault related attacks in cryptographic hardware, we presented a systematic method for designing single error correcting multiplier circuits for finite fields or Galois fields over GF(2m) in [7]. We used multiple parity predictions to correct single errors based on the Hamming principles. The problem with Hamming based error correction is the delay overhead. To mitigate the delay overhead, in this paper we present single error correction using Low Density Parity Check Codes (LDPC). The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. Our technique, when compared with existing techniques, gives better performance. We show that our Single Error Correction (SEC) multipliers over GF(2m) require slightly over 100 percent extra hardware, whereas with the traditional SEC techniques this figure is more than 200 percent.

In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as well as power efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that the 16% variation in threshold voltage results in negligible effects on static noise margin (SNM) during read operation. Experiments under different loading conditions indicate that there is reduction 2X (approximately) in power dissipation and 2X (approximately) in leakage.