A true random number generator (TRNG) is a fundamental component of hardware security. Latch-based TRNGs (LTRNGs), with their simple circuitry, are well-suited for energy-constrained IoT devices. However, a mismatch between the two inverters in the latch can result in little or no entropy output. This work presents chip measurement results demonstrating the use of negative bias temperature instability (NBTI) to mitigate mismatch in LTRNG. We propose a sequence to quantify the initial mismatch and selectively applying NBTI stress to PMOS device with higher conductivity for the first time. Measurement results in a 130nm CMOS process show that after 1000 minutes of NBTI stress at 3.0 V/120°C, the mismatches are reduced to within the overcompensated target of ±20 mV, and the output entropy improves from zero to over 0.85. Mismatch recovery at 20°C is negligible. Recovery at 120°C is accelerated, with mismatches still remaining below 50% of their initial values, and the output entropy remaining at 0.47 and 0.80 for the measured two chips. The randomness of post-processed data is validated using NIST SP 800-22 and SP 800-90B.

The demand for high energy efficiency in IoT devices continues to increase, necessitating the development of low energy consumption techniques to enhance the computation performance of these devices. In this study, we present a CMOS clock generator that operates at high operating voltage, achieves low frequency, and exhibits low power (LP) consumption, thus obviating the need for scaling-unfriendly step-down converters. The avoidance of step-down converters, which require passive components in their design, facilitates the development of scaling-friendly IoTs. The architecture of the prototype chip is composed of a voltage stacking and charge recycling design, which is achieved by the implementation of stacked oscillator and multiple frequency dividers in a configuration. The fabrication of the prototype chip is conducted using a 65-nm CMOS process. This work presents two configurations that are based on the concept of voltage stacking. The first configuration prioritizes LP consumption, yielding a clock generation of 2.09 Hz with a power of 0.22 nW at a voltage supply of 1.2 V and an operating range of 1.2–2.2 V. Notably, this configuration represents the lowest power achieved at a foundry-recommended nominal voltage in a sub-10-Hz clock generator. Another configuration is oriented toward generating low-frequency output signals, and the test chip attains an output frequency of 0.079 Hz and a supply voltage range of 0.88–1.3 V. The proposed architecture exhibits potential benefits in advanced technology nodes, particularly in the context of technology scaling.

True random number generators (TRNGs) are commonly used in hardware security for secure authentication, data encryption, etc. The raw random numbers often exhibit defects. The most commonly observed defects are bias and correlations. Post processing techniques have been developed to address them. The von Neumann method addresses bias, but it requires input that is uncorrelated and has an identical distribution. On the other hand, the Markov chain can address correlation but introduce bias. In this work, we research the lightweight combination of two techniques. We verified that MKV2(QL4)/VN2 performs well for both Markov and non-Markov model bitstreams. MKV1(QL8)/VN8W is effective for the Markov model. The randomness is verified by NIST SP 800-22 and 800-90B, and ENT, respectively. Both of these circuits require only 16 bits of memory, which is 12 times smaller than in previous work. MKV1(QL8)/VN8W is implemented using 65-nm CMOS. A prototype chip demonstrates a minimum energy consumption of 0.149 pJ/bit at 0.45V. When applied to a latch-based TRNG, it can double the operation frequency thanks to the enhanced decorrelation. The total energy consumption is reduced by 21%.

This article presents a true random number generator (TRNG) that achieves high entropy generation across wide voltage and temperature (VT) range (0.3–1.0 V, −40 °C to 110 °C) in a single latch-based entropy source (ES). In the ES, static inverter selection technique to minimize the mismatch between the paired inverters, and noise enhancement methods to increase the root mean square (rms) of noise voltage ($\sigma _{n}$) are implemented for good randomness and robustness. In a 130-nm CMOS technology, the TRNG occupies 5343$\mu \text{m} ^{\mathrm{ 2}}$and consumes 0.116 pJ/bit at 0.3 V including an on-chip von Neumann post-processing circuit. The cryptographic quality of TRNG’s output is verified by National Institute of Standards and Technology (NIST) SP800-22 tests. Up to 325 mV$V$pp noise injection attack tolerance is confirmed by power supply frequency injection attack. And an equivalent 20-year life at 0.3 V, 25 °C is verified by accelerated NBTI aging test.

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDDscaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDminof FFs is higher than the optimum supply voltage. In HVFF, the VDDof combinational logic gates is reduced below the VDDminof FFs while keeping the VDDof FFs at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.

For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-tree's latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (/spl sigma//sub v/spl I.bar/Local/). To achieve high-yield SRAM arrays in presence of random /spl sigma//sub v/spl I.bar/Local/ component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.

A new redundant binary (RB) architecture for a high-speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuitry or latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry-propagation circuit is constructed only with simple selector circuits. A 54/spl times/54-bit multiplier is designed using 0.5-/spl mu/m CMOS technology. A multiplication time of 8.8 ns is obtained by SPICE2 simulation for a supply voltage of 3.3 V which is the fastest that has been reported for 54/spl times/54-bit multipliers.>