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Nader Fathi

dblp:06/4904 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 72% Integrated circuit design · 28%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.011985
Algorithms for automatic transistor sizing in CMOS digital circuits · DAC 1985
Electronic design automation
physical design		 0.011985
Algorithms for automatic transistor sizing in CMOS digital circuits · DAC 1985
Electronic design automation › circuit sizing
transistor sizing		 0.011985
Algorithms for automatic transistor sizing in CMOS digital circuits · DAC 1985
Electronic design automation › timing analysis › path analysis
path delay analysis		 0.011985
Algorithms for automatic transistor sizing in CMOS digital circuits · DAC 1985
Electronic design automation
timing analysis		 0.011985
Algorithms for automatic transistor sizing in CMOS digital circuits · DAC 1985

Methods — techniques the papers use, named apart from their topics

delay modeling · 0.0area minimization · 0.0
YearPublicationVenuePosition
1985 Algorithms for automatic transistor sizing in CMOS digital circuits
abstract
This paper describes the algorithms for automatic transistor sizing (determination of device width and length) of CMOS digital circuits. In CMOS circuits, since power dissipation is small and not a limiting factor, the sizing algorithm is geared toward minimizing area. The program XTRAS (Xerox TRAnsistor Sizing Program) which determines transistor sizes as well as calculates path delays is described. Equations for the calculation of gate area, node capacitances, and rise and fall delays are given. Example circuits sized using XTRAS are compared and found to be within 10% of SPICE circuit simulations.
William H. Kao, Nader Fathi
 DAC2