We describe a binocular vision system that emulates disparity computation in the neuronal circuit of the primary visual cortex (V1). The system consists of two sets of silicon retinas and simple cell chips that correspond to the binocular vision and field programmable gate array (FPGA) circuit. This arrangement mimics the hierarchical architecture of the visual system of the brain. The silicon retina is an analog very large scale integrated (aVLSI) circuit and possesses a Laplacian-Gaussian-like spatial filter similar to the receptive field of the vertebrate retina. The simple cell chip generates a Gabor-like spatial filter similar to the orientation-selective receptive field of the simple cell in V1 by aggregating several pixels of the silicon retina. The FPGA receives the outputs from the two simple cell chips corresponding to binocular inputs from the left and right eyes and calculates the binocular disparity in real-time based on the disparity energy model. The system provides output images tuned to five different disparities in parallel. The disparity map is obtained by comparing these disparity energy outputs. Due to the combination of the parallel and analog computation of the aVLSIs and the pixel-wise computation with hard-wired digital circuits, the present system can efficiently compute the binocular disparity using compact hardware and low power dissipation in real-time.