This paper describes a variable gain WCDMA front-end receiver based on a direct conversion architecture in 0.18-μm CMOS. The front-end comprises a low noise variable gain amplifier (LNA) and a mixer. The LNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The front-end achieves a voltage conversion gain of 29.3 dB in the high gain mode of the LNA within 1-dB compression point dBm (iCP1dB) of -21 dBm. The front-end acquires an NF of 4.4 dB with an input return loss, S11, of -12.4 dB. The front-end achieves an in-band IIP3 of -6.16 dBm. The integrated LNA and mixer consumes approximately 9.2 mA of current from a 1.8-V power supply.

This paper describes a senior/graduate level course in hardware logic verification being offered by The Ohio State University in cooperation with IBM. The need for the course is established through the growing importance of logic verification to users of custom logic designs. We discuss the short-term and long-term goals for the course, and describe the course content and format. The course relies heavily on lab projects to illustrate the main concepts. Three projects and a final project review are described.

Existing and emerging layer-4 switching technologies require packet classification to be performed on more than one header field, known as layer-4 lookup. Currently, the fastest general layer-8 lookup scheme delivers a throughput of 1 million lookups per second (MLPS), far off from 25/75 MLPS needed to support 50/150 Gbps layer-4 router. We propose the use of route caching to speed up layer-4 lookup, and design and implement a cache architecture for this purpose. We investigated the locality behavior of the Interent traffic (at layer-4) and propose a near-LRU algorithm that can best harness this behavior. In implementation, to best approximate fully-associative near-LRU using relatively inexpensive set-associative hardware, we invented a dynamic set-associative scheme that exploits the nice properties of N-universal hash functions. The cache architecture achieves a high and stable hit ratio above 90 percent and a fast throughput up to 75 MLPS at a reasonable cost.