A novel architecture suitable for FPGA/ASIC implementation of a video scalar is presented. The scheme proposed here results in enormous savings of memory normally required, without compromising on the image quality. In the present work, SVGA compatible video sequence is scaled up to XGA format. The up scaling operation for a video sequence is carried out by scaling up the image input, followed by down scaling and filtering. The FPGA implementation of the proposed video-scaling algorithm is capable of processing high-resolution, color pictures of sizes up to 1024x768 pixels at the real time video rate of 30 frames/second. The design has been realized by RTL compliant Verilog coding, and fits into a single chip with a gate count utilization of two million gates. For lower resolution pictures, the mapped device can be scaled down. The present FPGA implementation compares favorably with another ASIC implementation.

A novel block matching algorithm for motion estimation in a video frame sequence, well suited for a high performance FPGA implementation is presented in this paper. The algorithm is up to 40% faster when compared to one of the fastest existing algorithms, viz., one-at-a-time step search algorithm without compromising either in the image quality or in the compression effected. The speed advantage is preserved even in the event of a sudden scene change in a video sequence. The proposed algorithm is also capable of dynamically detecting the direction of motion of image blocks. The FPGA implementation of the algorithm is capable of processing color pictures of sizes up to 1024x768 pixels at the real time video rate of 25 frames/second and conforms to MPEG-2 standards.

This paper proposes an efficient implementation of a Programmable Pruning Level Control (PPLC) based video encoder for real time image compression applications. The implementation is capable of processing good quality monochrome images of sizes up to 1200/spl times/1024 pixels and color images 1024/spl times/1024/spl times/768 pixels, both at the rate of 25 frames per second. The design fits into two pieces of a commercially available Embedded Programmable Logic Devices (EPLDs) and can be used directly as a coprocessor on a PC bus.

This paper proposes an effective implementation of Variable Length Coder (VLC) for image compression using an Embedded Programmable Logic Device (EPLD) to meet the real time requirements. The scheme has features such as header information and color processing not found in earlier implementations. It has a throughput of 50 Mbps at 50 MHz clock rate. The design fits into just one piece of a commercially available EPLD and is capable of processing monochrome images of sizes up to 1024/spl times/768 pixels and color images of up to 67% of this size, both at the rate of 25 frames per second.