Boundary-Scan (B-S) has been widely used for interconnect testing. It allows all pins of a B-S chip to be controlled uniformly by either system or B-S logic. The requirement that all pins are controlled by the same logic limits B-S usage for many applications. We propose a new B-S instruction, called PINCONTROL, to allow mixed control of chip pins. That is, each pin can be individually configured to be controlled by the system or B-S logic. In this paper we shall demonstrate the application of this instruction for fault injection and inter-chip path delay testing.

We present algorithms for generating and applying backplane interconnect test in a boundary-scan environment. Several unique characteristics distinguish backplane interconnect test from intra-board interconnect test. We address these special characteristics and provide a solution that reduces test data volume, accommodates dynamic backplane configuration, resolve test synchronization issue and supports uses of different board technologies. We propose a walking-enable test algorithm that guarantees high fault coverage and fine diagnosis resolution. The simplicity of the walking-enable test algorithm enables straightforward implementations. Other algorithms are also presented to provide trade-offs between test application time,fault coverage and diagnosis resolution. The proposed algorithms can also be used for testing cables that connect boards or backplanes.

The four (five) wires defined in IEEE Std 1149.1 can be extended to the backplane to form a test bus that provides a linkage between 1149.1 boards and the backplane environment. This test architecture has many advantages. However, one of the disadvantages is its inability to detect errors that may occur during backplane data transmission and to protect the boards-under-test from unsafe corrupted data. In this paper, we propose a novel scheme to address these issues. The concept is first described, then followed by implementation examples. As a result of its simplicity and flexibility, the proposed scheme can be implemented in different ways to suit specific application needs.

This paper investigates the relationship between path-delay-fault testability and multiple stuck-at-fault testability in multilevel combinational circuits. It is shown that a complete robust path-delay-fault test set may not detect all multiple stuck-at faults in multilevel circuits. We also show that path-delay-fault testability does not imply multiple stuck-at-fault testability in multilevel circuits, contradicting a recent paper. Certain path delay tests are also shown to be invalidated by the presence of untestable or untested multiple stuck-at faults.

We address the problem of testing circuits for temporal correctness. A circuit is considered delay-verifiable if its timing correctness can be established by applying delay tests. It is shown that verifying the timing of a circuit may require tests which can detect the simultaneous presence of more than one path delay fault. We provide a general framework for examining delay-verifiability by introducing a special class of faults called primitive path delay faults. It is necessary and sufficient to test every fault in this class to ensure the temporal correctness of combinational circuits. Based on this result, we develop a synthesis procedure for combinational circuits that can be tested for correct timing. Experimental data show that such implementations usually require less area than completely delay testable implementations.>

In this paper we show that any finite state machine can be implemented by a fully path-delay-fault testable nonscan sequential circuit. Synthesis methods are proposed, which use a one-hot encoding of states, a special circuit structure and at most one additional input. Combined with existing synthesis techniques for delay-fault testable combinational circuits, these methods can produce nonscan sequential circuits in which every path has a robust or validatable nonrobust test.>

We show that most symmetric functions do not have delay-testable two-level implementations. A method of transforming any untestable minimal two-level implementation of a symmetric function into a delay-testable three- or four-level one using the distributive law is presented.>

It is shown that verifying the timing of a circuit by testing may require tests which can detect the simultaneous presence of more than one path delay fault. We introduce a special class of path delay faults, called primitive faults, whose detection is shown to be necessary and sufficient to ensure the temporal correctness of a circuit. Using this result, we develop a synthesis procedure for combinational circuits that can be tested for correctness of timing. Experimental data show that such implementations usually require less area than completely delay testable implementations.>

We present a new approach to synthesizing fully path-delay-fault testable non-scan sequential circuits. Two methods are proposed. Given the state transition graph of a finite state machine, one of our methods generates a fully robustly testable circuit while the other method, which may lead to more area-efficient circuits, guarantees robust or validatable non-robust tests for all paths.>

The performance of a fast fault simulation algorithm for combinational circuits, such as the critical-path-tracing method, is determined primarily by the efficiency with which it can deduce the detectability of stem faults (stem analysis). A graph-based approach to perform stem analysis is proposed. A dynamic data structure, called the criticality constraint graph, is used during the backward pass to carry information related to self-masking and multiple-path sensitization of stem faults. The structure is updated in such a way that when stems are reached, their criticality can be found by looking at the criticality constraints on their fanout branches. Compared to the critical-path-tracing method, the algorithm is exact and does not require forward propagation of individual stem faults. Several examples which illustrate the power of the algorithm are given. Preliminary data on an implementation are also provided.>