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M. Vergniault

dblp:06/6419 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1980
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.011980
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability · IEEE Trans. Computers 1980
Electronic design automation › hardware test
integrated circuit testing		 0.011980
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability · IEEE Trans. Computers 1980
Electronic design automation › hardware verification and test
fault modeling		 0.011980
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability · IEEE Trans. Computers 1980

Methods — techniques the papers use, named apart from their topics

test classification · 0.0
YearPublicationVenuePosition
1980 Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
abstract
At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior.
J. Galiay, Yves Crouzet, M. Vergniault
 IEEE Trans. Computers3