Average power analysis plays a crucial role in the design of large-scale digital integrated circuits (ICs). The integration of data-driven machine learning (ML) methods into the electronic design automation (EDA) fields has increased the demand for extensive datasets. To address this need, we propose a novel pseudo-circuit generation algorithm rooted in graph topology. This algorithm efficiently produces a multitude of power analysis examples by converting randomly generated directed acyclic graphs (DAGs) into gate-level Verilog pseudo-combinational circuit netlists. The subsequent introduction of register units transforms pseudo-combinational netlists into pseudo-sequential circuit netlists. Hyperparameters facilitate the control of circuit topology, while appropriate sequential constraints are applied during synthesis to yield a pseudo-circuit dataset. We evaluate our approach using the mainstream power analysis software, conducting pre-layout average power tests on the generated circuits, comparing their performance against benchmark datasets, and verifying the results through circuit topology complexity analysis and static timing analysis (STA). The results confirm the effectiveness of the dataset, and demonstrate the operational efficiency and robustness of the algorithm, underscoring its research value.

The performance of complementary metal oxide semiconductor (CMOS) circuits is affected by electromagnetic interference (EMI), and the study of the circuit’s ability to resist EMI will facilitate the design of circuits with better performance. Current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process; their EMI resistance performance deserves further study. This paper introduces three kinds of NOT gate circuits: conventional voltage-mode CMOS, MOS current-mode logic (MCML) with voltage signal of input and output, and current-mode CMOS with current signal of input and output. The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation, and a disturbance level factor is defined to compare the effects of different interference terminals, interference signals’ waveforms, and interference signals’ frequencies on the circuits in the 65 nm process. The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits. Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies, and the higher the operating frequency of the current-mode CMOS circuits, the better the resistance performance of the circuits to EMI. Additionally, the effects of different temperatures and different processes on the resistance performance of three circuits are also studied. In the temperature range of −40 °C to 125 °C, the higher the temperature, the weaker the resistance ability of voltage-mode CMOS and MCML circuits, and the stronger the resistance ability of current-mode CMOS circuits. In the 28 nm process, the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits. The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process, while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process. This study provides a basis for the design of current-mode CMOS circuits against EMI.

Place recognition plays a crucial role in relocalization and loop closure detection tasks for robots and vehicles. This paper seeks a well-defined global descriptor for LiDAR-based place recognition. Compared to local descriptors, global descriptors show remarkable performance in urban road scenes but are usually viewpoint-dependent. To this end, we propose a simple yet robust global descriptor dubbed FreSCo that decomposes the viewpoint difference during revisit and achieves both translation and rotation invariance by leveraging Fourier Transform and circular shift technique. Besides, a fast two-stage pose estimation method is proposed to estimate the relative pose after place retrieval by utilizing the compact 2D point clouds extracted from the original data. Experiments show that FreSCo exhibited superior performance than contemporaneous methods on sequences of different scenes from multiple datasets. Code will be publicly available at https://github.com/soytony/FreSCo.

Precise web page classification can be achieved by evaluating features of web pages, and the structural features of web pages are effective complements to their textual features. Various classifiers have different characteristics, and multiple classifiers can be combined to allow classifiers to complement one another. In this study, a web page classification method based on heterogeneous features and a combination of multiple classifiers is proposed. Different from computing the frequency of HTML tags, we exploit the tree-like structure of HTML tags to characterize the structural features of a web page. Heterogeneous textual features and the proposed tree-like structural features are converted into vectors and fused. Confidence is proposed here as a criterion to compare the classification results of different classifiers by calculating the classification accuracy of a set of samples. Multiple classifiers are combined based on confidence with different decision strategies, such as voting, confidence comparison, and direct output, to give the final classification results. Experimental results demonstrate that on the Amazon dataset, 7-web-genres dataset, and DMOZ dataset, the accuracies are increased to 94.2%, 95.4%, and 95.7%, respectively. The fusion of the textual features with the proposed structural features is a comprehensive approach, and the accuracy is higher than that when using only textual features. At the same time, the accuracy of the web page classification is improved by combining multiple classifiers, and is higher than those of the related web page classification algorithms.

Conventional intrusion detection systems based on supervised learning techniques require a large number of samples for training, while in some scenarios, such as zero-day attacks, security agencies can only intercept a limited number of shots of malicious samples. Therefore, there is a need for few-shot detection. In this paper, a detection method based on a meta-learning framework is proposed for this purpose. The proposed method can be used to distinguish and compare a pair of network traffic samples as a basic task of learning, including a normal unaffected sample and a malicious one. To accomplish this task, we design a deep neural network (DNN) named FC-Net, which mainly comprises two parts: feature extraction network and comparison network. FC-Net learns a pair of feature maps for classification from a pair of network traffic samples, then compares the obtained feature maps, and finally determines whether the pair of samples belongs to the same type. To evaluate the proposed detection method, we construct two datasets for few-shot network intrusion detection based on real network traffic data sources, using a specifically developed approach. The experimental results indicate that the proposed detection method is universal and is not limited to specific datasets or attack types. Training and testing on the same datasets demonstrate that the proposed method can achieve the average detection rate up to 98.88%. The outcome of training on one dataset and testing on the other one confirms that the proposed method can achieve better performance. In a few-shot scenario, malicious samples in an untrained dataset can be detected successfully, and the average detection rate is up to 99.62%.

To simplify the process for identifying 12 types of symmetric variables in Boolean functions, we propose a new symmetry detection algorithm based on minterm expansion or the truth table. First, the order eigenvalue matrix based on a truth table is defined according to the symmetry definition of a logic variable. By analyzing the constraint conditions of the order eigenvalue matrix for 12 types of symmetric variables, an algorithm is proposed for identifying symmetric variables of the Boolean function. This algorithm can be applied to identify the symmetric variables of Boolean functions with or without don’t-care terms. The proposed method avoids the restriction by the number of logic variables of the graphical method, spectral coefficient methods, and AND-XOR expansion coefficient methods, and solves the problem of completeness in the fast compu-tation method. The algorithm has been implemented in C language and tested on MCNC91 benchmarks. The application results show that, compared with the traditional methods, the new algorithm is an optimal detection method in terms of the applicability of the number of logic variables, the Boolean function including don’t-care terms, detection type, and complexity of the identification process.

Compared with complementary metal–oxide semiconductor (CMOS), the resonant tunneling device (RTD) has better performances; it is the most promising candidate for next-generation integrated circuit devices. The universal logic gate is an important unit circuit because of its powerful logic function, but there are few function synthesis algorithms that can implement an n-variable logical function by RTD-based universal logic gates. In this paper, we propose a new concept, i.e., the truth value matrix. With it a novel disjunctive decomposition algorithm can be used to decompose an arbitrary n-variable logical function into three-variable subset functions. On this basis, a novel function synthesis algorithm is proposed, which can implement arbitrary n-variable logical functions by RTD-based universal threshold logic gates (UTLGs), RTD-based three-variable XOR gates (XOR3s), and RTD-based three-variable universal logic gate (ULG3s). When this proposed function synthesis algorithm is used to implement an n-variable logical function, if the function is a directly disjunctive decomposition one, the circuit structure will be very simple, and if the function is a non-directly disjunctive decomposition one, the circuit structure will be simpler than when using only UTLGs or ULG3s. The proposed function synthesis algorithm is straightforward to program, and with this algorithm it is convenient to implement an arbitrary n-variable logical function by RTD-based universal logic gates.

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

Traditional CMOS technology faces some fundamental physical limitations. Therefore, it has become very important for the integrated circuit industry to continue to develop modern devices and new design methods. The threshold logic gate has attracted much attention because of its powerful logic function. The resonant tunneling diode (RTD) is well suited for implementing the threshold logic gate because of its high-speed switching capability, negative differential resistance (NDR) characteristic, and functional versatility. In this paper, based on the Reed-Muller (RM) algebraic system, a novel method is proposed to convert three-variable non-threshold functions to the XOR of multiple threshold functions, which is simple and has a programmable implementation. With this approach, all three-variable non-threshold functions can be presented by the XOR of two threshold functions, except for two special functions. On this basis, a novel three-variable universal logic gate (ULG3) is proposed, composed of two RTD-based universal threshold logic gates (UTLG) and an RTD-based three-variable XOR gate (XOR3). The ULG3 has a simple structure, and a simple method is presented to implement all three-variable functions using one ULG3. Thus, the proposed ULG3 provides a new efficient universal logic gate to implement RTD-based arbitrary n-variable functions.

An addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper we propose a novel 1-bit full adder cell which uses only eight transistors. In this design, three multiplexers and one inverter are applied to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay, and power-delay produced using the new design are analyzed and compared with those of other designs using HSPICE simulations. The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value. The low power and low transistor count make the novel 8T full adder cell a candidate for power-efficient applications.

By analysing the principle of multi-thresholded neurons (MTNs), a methodology is developed for designing multi-thresholded neuron circuits (MTNCs). First, two n-channel MOS transistors are employed to design the voltage-mode synapse circuit with high simplicity and linearity. Second, a BiCMOS technique based circuit named judgement-converting switch (JCS) is proposed. The JCS whose threshold is voltage-controlled current signal, provides an ability of converting the voltage signal to current signal. Based on this possibility, an approach is put forward to design multi-thresholded judgement function circuits (MTJFCs). Finally, single MTNC is designed for implementing XOR operation at switch level. Simulation results with PSPICE show that the designed circuits not only have the correct logic function but also small propagation delay.