The problem of power-delay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the short-circuit power are considered, and a new modeling technique is used to calculate the short-circuit power. The notion of transition density is used, with an enhancement that considers the effect of gate delays on the transition density. When the short-cuircuit power is neglected, the minimum power circuit is idential to the minimum area circuit. However, under our more realistic models, our experimental results on several circuits show that the minimum power circuit is not necessarily the same as the minimum area circuit.

The problem of sizing gates for power-delay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimum power circuit is not necessarily the minimum-sized circuit.

A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient algorithm for combinational circuits, we examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Experimental results show that by formulating gate size selection together with the clock skew optimization as a single optimization problem, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. Finally, we address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.>

The contribution of this paper on the diagnosis (fault location) of CMOS bridging faults is threefold: First, the traditional fault dictionary (referred to as the full dictionary in this paper) is evaluated at the circuit level using a mixed-mode fault simulator. The fault set consists of randomly-generated gate input/output bridging faults. By using mixed-mode gate- and electrical-level detection methods, good diagnostic capability is achieved using only gate-level generated test sets. Second, we evaluate two reduced fault dictionaries, the pass/fail dictionary and the count dictionary. Finally, the effectiveness of I/sub DDQ/ for diagnosis is examined. The results show that I/sub DDQ/, combined with the proposed voltage detection methods, achieves the highest diagnostic performance, with nearly complete diagnosis.>

In this paper, we rst present an e cient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure isembedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As aresult, the algorithm is able to obtain superior solutions. 1

The contribution of this paper on the diagnosis (fault location) of CMOS bridging faults is threefold: First, the traditional fault dictionary (referred to as the full dictionary) is evaluated at the circuit level using a mixed-mode fault simulator. The fault set consists of randomly-generated gate input/output bridging faults. By using detection methods good diagnostic capability is achieved using only gate-level generated test sets. Second, the authors evaluate two reduced fault dictionaries, the pass/fail dictionary and the count dictionary. The results show the performance of the much smaller pass/fail dictionary is nearly equal to the full dictionary. Third, the effectiveness of I/sub DDQ/ for diagnosis is examined. The results show that I/sub DDQ/ combined with the proposed voltage detection methods achieves the highest diagnostic performance, with near complete diagnosis.>

This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standard-cell paradigm. This is effected by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Traditional methods treat these two problems separately, which may lead to very sub-optimal solutions in some cases. Experimental results show that by considering the two problems together, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

An algorithm is presented which estimates the rotation speed of an orbiting point in spotlight-mode synthetic aperture radar (SAR) systems. Current reconstruction algorithms for spotlight-mode SAR assume that the relative motion between radar and the object is known at all time instants. Although this is true, for example, for airborne terrain mapping radar, the assumption may not apply to all cases. For ground-based radar which is imaging an unidentified space object such as a satellite, the rotation speed of the object is usually unknown. Furthermore, for computer vision applications it is also very important to estimate the rotation speed for the purpose of motion estimation. The new algorithm can accurately estimate the rotation speed in most cases. Simulation results show that the average estimation error is less than 0.78%. For 99.33% of the cases, the estimation error is less than 3%. In the worst case, the error is still less than 6.68%. >