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Pamela Castalino

dblp:06/8314 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Mathematical optimization · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Mathematical optimization
multi-objective optimization
0.112010
Pareto sampling: choosing the right weights by derivative pursuit · DAC 2010
Integrated circuit design › memory circuit design
SRAM cell design
0.012010
Pareto sampling: choosing the right weights by derivative pursuit · DAC 2010

Methods — techniques the papers use, named apart from their topics

simplicial approximation · 0.2derivative pursuit · 0.2convex weighted-sum method · 0.2
YearPublicationVenuePosition
2010 Pareto sampling: choosing the right weights by derivative pursuit
abstract
The convex weighted-sum method for multi-objective optimization has the desirable property of not worsening the difficulty of the optimization problem, but can lead to very nonuniform sampling. This paper explains the relationship between the weights and the partial derivatives of the tradeoff surface, and shows how to use it to choose the right weights and uniformly sample largely convex tradeoff surfaces. It proposes a novel method, Derivative Pursuit (DP), that iteratively refines a simplicial approximation of the tradeoff surface by using partial derivative information to guide the weights generation. We demonstrate the improvements offered by DP on both synthetic and circuit test cases, including a 22 nm SRAM bitcell design problem with strict read and write yield constraints, and power and performance objectives.
Amith Singhee, Pamela Castalino
DAC2