In this work, a compact broadband patch antenna integrated with an Artificial Magnetic Conductor (AMC) structure is proposed for WiMAX$(3.6 / 4.8 \text{GHz})$and WLAN (5.1/5.825 GHz) 5G applications. The antenna, fed by a 50Ω microstrip line, consists of a partial ground$(0.035 ~\text{mm})$, an FR4 substrate$\left(\varepsilon_{r}=4.4\right.$, thickness$=1.6 ~\text{mm}$, loss tangent = 0.025), and a rectangular patch with parasitic elements and an elliptical slot. It achieves a wide impedance bandwidth of 3.03 GHz within a compact size of$26.5 \times 29 \times 1.6 ~\text{mm}^{3}$. A$4 \times 4 \text{AMC}$array is placed on the back to suppress back radiation lobes and enhance gain. The overall antenna size is$40 \times 40 \times 10.4 ~\text{mm}^{3}$. Simulated and measured results confirm a bandwidth from 3.62 to 6.65 GHz, with a peak gain of 10 dB at 6 GHz and 8.5 dB at 5.8 GHz, making it a promising candidate for WiMAX and WLAN$\mathbf{5 G}$systems.

The ongoing integration of advanced functionalities in contemporary system-on-chips (SoCs) poses significant challenges related to memory bandwidth, capacity, and thermal stability. These challenges are further amplified with the advancement of artificial intelligence (AI), necessitating enhanced memory and interconnect bandwidth and latency. This article presents a comprehensive study encompassing architectural modifications of an interconnect-dominated many-core SoC targeting the significant increase of intermediate, on-chip cache memory bandwidth and access latency tuning. The proposed SoC has been implemented in 3-D using A10 nanosheet technology and early thermal analysis has been performed. Our workload simulations reveal, respectively, up to 12- and 2.5-fold acceleration in the 64-core and 16-core versions of the SoC. Such speed-up comes at 40% increase in die-area and a 60% rise in power dissipation when implemented in 2-D. In contrast, the 3-D counterpart not only minimizes the footprint but also yields 20% power savings, attributable to a 40% reduction in wirelength. The article further highlights the importance of pipeline restructuring to leverage the potential of 3-D technology for achieving lower latency and more efficient memory access. Finally, we discuss the thermal implications of various 3-D partitioning schemes in High Performance Computing (HPC) and mobile applications. Our analysis reveals that, unlike high-power density HPC cases, 3-D mobile case increases$T_{\max }$only by$2~^{\circ } $C–$3~^{\circ } $C compared to 2-D, while the HPC scenario analysis requires multiconstrained efficient partitioning for 3-D implementations.

This paper presents an investigation of System-on-Chip (SoC) communication latency optimization for 3D system integration and highlights the role of architectural modifications to maximize the Power, Performance, & Area (PPA) benefits. An instance of a highly configurable RISC-V SoC is implemented using ∼2nm nanosheet technology and different 3D stacking options using design flow from sign-off tools. The proposed implementation targets performance optimization for different 3D partitioning scenarios: Memory-on-Logic (MoL) & Logic-on-Logic (LoL). We target 2-die 3D Integrated Circuits (3D-IC) with high density 3D interconnect using Face-to-Face (F2F) hybrid bonding (∼1µm), and 3-die stack, as Face-to-Back (F2B) on top of F2F. Our analysis of the 16-core SoC instance shows that the proposed architectural optimizations bring a significant reduction of 4 pipeline stages in the design hierarchy at a marginal cost of 9% effective frequency loss when implemented in 3D in comparison to the baseline 2D architecture. Further, going from 2D to 3D allows more than 40% total system wire-length reduction & 10% less cell area, resulting in 20% power savings. These findings hold promise for further explorations on many-core SoC instances (256 & more) facing system interconnect challenges.

The rapid expansion of the electric vehicle sector presents a transformative opportunity for sustainable transportation, offering reduced emissions and increased energy efficiency. This paper introduces an innovative architecture leveraging the Internet of Things to enhance the maintenance and real-time monitoring of electric vehicles. The proposed system collects data from various sensors within the EV, including battery health, motor performance, and operational metrics. Machine learning models process this data in real-time, predicting maintenance needs before they become critical issues. Cloud integration enables remote monitoring and data accessibility, fostering a collaborative ecosystem. This architecture promises to elevate the reliability, efficiency, and sustainability of the EV industry, harnessing digitization and data-driven insights for cleaner, smarter, and more reliable transportation.

Event-driven neuromorphic processors for artificial intelligence (AI) inference on edge/IoT devices require largeon-chip memory capacity, for efficient execution of spiking neural networks (NNs). In this work, we evaluate 3-D stacking benefits on SENECA, a digital neuromorphic accelerator core, sweeping itson-chip memory capacity from 2 up to 32 Mb in both legacy planar and advanced nanosheet CMOS logic nodes. In a planar CMOS node (GF-22 nm), two-die memory-on-logic (MoL) partitioning enables$8\times $moreon-chip memory, and it boosts operating frequency by 7% with 26% less power than the 2-D. Moving to an advanced nanosheet technology (imec A10), multidie (up to 7 dies) MoL stacking enables a performance increase of up to 29% and power savings up to 31%. Furthermore, a core folding (CF) partitioning in A10 shows up to 16% performance improvement with 12% total power savings with respect to the 2-D implementation on the same technology. We also demonstrate no thermal overhead for multidie stacking at advanced nodes for designs exhibiting low power density. These physical design explorations lay the foundation for system technology co-optimization studies for edge devices.

This paper suggests a broadband, high gain, large coverage 1×4-array antenna for 2.45 GHz radio frequency identification (RFID) reader applications. Initially, to maintain the compactness, a miniaturized basic patch element is designed with minimal return loss, good gain and high radiation efficiency. Based on the miniaturized single patch element, an array antenna with lx2 configuration has been designed and optimized. Afterwards, a hybrid coupler is used to feed the radiating patches of the miniaturized lx2 array antenna. The proposed antenna offers broadband radiation characteristics with a high gain, high radiation efficiency, and switchable main beams due to the proposed arrangement of the feeding network. Morever, it generates flexible beam directions having an extensive broad operating ranging from 1.725 GHz to 2.960 GHz with an impedance bandwidth of 1250 MHz, peak gain and radiation efficiency of 11.26 dB, and 99.52%, respectively. It can also radiate in two different regions (−30° & + 30°) by switching the connected ports of the two input feeds of the hybrid coupler. The structural design has been executed on a 1.56 mm thick Rogers RT/duroid 5880 Substrate with a physical area of 240×136mm2with the help of the HFSS simulator. The results achieved with HFSS software are re-verified by CST simulator.

In this paper, we discuss continuous time periodic debugging of a software, in which faults are corrected, instead of at the instants of their detection, at some prespecified times. We describe maximum-likelihood estimation for the model parameters assuming exponential distribution for the time between successive occurrence of a fault, which can be used to estimate the reliability of the software. We also derive the asymptotic properties of the estimated model parameters, specially the number of faults initially present in the software. We investigate the finite sample properties of the estimators, specially that of the number of faults, through simulation. Finally, we analyze a dataset obtained from the testing of a flight control software.