As silicon photonic integrated circuits (PICs) increase in complexity, ensuring their reliability against manufacturing and operational variations necessitates robust Design-for-Test (DfT) strategies. We present an adaptable methodology for DfT insertion in large-scale PICs, centered on physics-informed hypergraph partitioning. Our approach uniquely leverages hypergraph-based weighting derived from process sensitivities (e.g. etch, doping) and operational drifts (e.g. thermal, injection), quantified using partial derivatives from foundry data or Transfer Matrix Method (TMM) simulations. This assigns actionable risk values to both devices (nodes) and interconnects (hyperedges). We employ k-way partitioning to achieve finer sub-network isolation and targeted test access, crucial for vulnerability localization in complex PICs like multi-level ring resonator networks or large MZI-based crossbars. Experiments performed on PIC designs demonstrate the application of the proposed risk coverage metric to vulnerability localization and test point insertion, achieved with quantifiable and moderate overhead.

This paper proposes a design-for-test (DFT) methodology and architecture for testing and validation of silicon photonic integrated circuits (PICs). We describe the design of silicon photonic circuits and components that comprise the proposed DFT architecture. The designs are extensively simulated and validated as test-access and fault-detection circuitry. We demonstrate how the DFT approach can be deployed on photonic integrated circuits and how they can be tested for correct operation, in terms of signal power and phase. The application is demonstrated on two distinct types of designs – an optical neural network comprising optical devices in a feed-forward topology, and an optical logic circuit with feedback loops.

Photonic ring-resonators are key components of many on-chip optical-interconnect wavelength division multiplexing (WDM) network architectures. Thermal interactions between on-chip heat-sources and ring resonators pose significant operational and integration challenges, as these devices are extremely sensitive to temperature-induced changes in refractive index. Contemporary literature proposes active compensation for such refractive index variations (e.g. carrier-injection based tuning and/or WDM channel remapping); however, these are costly in terms of power and area. This paper presents a thermal-aware synthesis approach for ring-resonator compensation. We show how ring-resonators are analyzed in the presence of external thermal gradients, and employ a perturbation analysis to derive an equivalent, trimming-enabled, ring-resonator design. Our methodology produces a design-template that can be used to compensate for thermal variations through modifications to the waveguide's geometric structure. This approach complements active compensation techniques, and the synthesis is compatible with contemporary lithographic methods. Using this approach, we perform design space exploration with respect to variations to the waveguide structure and their effect on the range and precision of thermal compensation.

Increasing scope and applications of integrated optics necessitates the development of automated techniques for physical design of optical systems. A key area of integrated optic design is waveguide routing, which currently lacks the level of automation found in VLSI design. Unlike VLSI, where signal nets are routed with metal layers and vias, integrated optics is a planar technology and lacks the inherent signal restoration capabilities of static-CMOS. Waveguides suffer signal loss due to planar (perpendicular) waveguide crossings and also from sharp bends. Therefore, in contrast to area or wire length, signal loss minimization - as a function of waveguide crossings and bends - is a primary objective of any routing solution. Our studies show that waveguide routing problems can be suitably formulated as planar channel routing. This paper investigates channel routing for integrated optical waveguides fabricated in a planar substrate. We present routing techniques where crossings, bends, and area are accounted for in an integrated solution. Two distinct channel routing techniques are presented: 1) a new channel router based on net sorting and utilizing non-Manhattan routing grids and 2) a router based on crossing-aware graph-constrained track assignment that also exploits waveguide curves to improve track utilization. Both techniques are crossing-minimal, and are also constrained suitably to reduce bend loss and area. We compare and evaluate the performance of our channel routers on a number of optical design benchmarks.

As silicon photonics technology matures, optical devices will be available on a scale never before seen or utilized. It is therefore imper-ative to develop automated methods for synthesizing optical devices for large-scale designs. We present design and synthesis method-ologies for implementing digital logic using conventional integrated optical components, specifically optical cross-bar routing devices based on Mach-Zehnder Interferometry. Our design methodologies utilize the unique advantages of these optical devices, while also addressing the limitations of the technology. We extend these design concepts to include technology-specific logic sharing, and provide automated techniques for logic design implementation, evaluating the efficacy of our techniques on a number of logic designs. Through the convergence of communications and computing, optical devices are utilized on scales beyond traditional optic design.