Operating in the near-threshold regime can result in significant energy savings. Unfortunately, the increased timing variation prevents conventional error-detection techniques from properly functioning. This paper introduces two circuit-level timing error detection techniques that aim to increase throughput while operating in the near-threshold voltage regime: current-sensing completion detection and transition-aware completion detection. Each method allows any digital circuit to operate at speeds not limited by the worst-case critical path. Throughput improvements and energy savings are reported for implementations on a 16-bit adder.

A two-channel micro-power incremental ADC, designed for biosensor interface circuits, is reported. It uses a noise-coupled multi-bit delta-sigma loop, integrated with a novel digital decimation filter operating in near-threshold. It was realized in the IBM 90 nm CMOS technology. The fabricated 90nm CMOS prototype device, for a 1 Vppdifferential input range, experimentally shows a 74dB SNDR up to 2 kHz (1 kHz/channel) signal bandwidth. The total measured power consumption of the modulator is 13.5 μW.

A power/area aware design is mandatory for the MIMO (Multi-Input Multi-Output) detectors used in LTE and WiMAX standards. The 64-QAM modulation used in the MIMO detector requires more detection effort compared to the smaller constellation sizes widely implemented in the literature. In this work we propose a new architecture for the K-best detector, which unlike the popular multi-stage architecture used for K-best detectors, implements just one core. Also, we introduce a slight modification to the K-best algorithm that reduces the number of multiplications by 44%, and reduces the total power consumption by 27%, without any noticeable performance degradation. The overall architecture consumes only 24KGate, which is the smallest area compared to the other implementations in the literature. It also results in an at least 4-fold greater throughput-efficiency (Mbps/KiloGate) compared to the other detectors, while consuming a small power. The decoder implemented in a commercial 130nm process provides a data-rate of 107Mbps, and consumes 54.4mW.