In this paper, an analog front-end (AFE) local-field potential (LFP) acquisition unit with real-time stimulation artifact removal is proposed and verified for closed-loop deep brain stimulation (DBS) applications. The proposed acquisition unit is called the synchronized sample-and-hold stimulation artifact blanking (SSAB) AFE LFP acquisition unit. Both right-leg-driven (RLD) circuit and monopolar electrode-tissue impedance (ETI) measurement circuit associated with the AFE amplifier are also proposed. During closed-loop stimulations, the artifact removal is realized through the SSAB-IPC by blanking the AR-CCIA with a clock synchronized to the stimulation-enable signal and holding the amplifier at its state before stimulation through a sample-and-hold operation. After stimulation, the acquisition unit can quickly recover from the holding state back to the LFP recording state to reduce the discontinuity in LFP recording. The proposed acquisition unit was fabricated in 0.18-$\mu {\mathrm{ m}}$CMOS technology. With the RLD circuit, the measured CMRR is 124– 145 dB in the signal bandwidth. The fabricated monopolar ETI measurement circuit has a measurement error less than 8.3% with an extra power consumption of$2.65 \mu \text{W}$. The experimental results have shown that the proposed SSAB AFE LFP acquisition unit is feasible for the integration of SoCs in real-time closed-loop DBS systems for various applications.

In this paper, a 65nm-CMOS 8-channel Analog Front-End (AFE) acquisition circuit is designed and fabricated for long term EEG monitoring. The Capacitively-Coupled Chopper Instrumentation Amplifier (CCCIA) with chopper modulation is used to amplify input EEG signals and suppress flicker noise. To realize low high-pass corner and large Electrode DC Offset (EDO) rejection ability, a fast-settling Hybrid DC Servo Loop (HDSL) is proposed here. It contains Digital DSL (DDSL) and Analog DSL (ADSL) to achieve better trade-off among power consumption, area, and hardware complexity. An energy-efficient 10-bit SAR ADC with offset-calibration comparator is integrated for accurate A/D conversion. The chip is fabricated in 65nm CMOS technology. The measured overall power dissipation of the acquisition circuit is 1.97μW per channel. The input-referred noise of AFE Amplifier (AFEA) is 0.7μV in pass band, and the Noise Efficient Factor (NEF) of the CCCIA is 1.99. The measured HDSL calibration time is 125ms. The fabricated SAR ADC has the power consumption of 0.85μW under 1V supply and the SNDR of 59.8dB at 100kS/s with the Nyquist input frequency. This chip can record EEG signals successfully and the recorded signal has been verified by NeruScan SynAmps RT 64-channel amplifiers.

A 13.56MHz high efficiency CMOS 1X/3X active rectifier with a novel active triple-voltage(3X) rectifier is proposed and verified. The proposed rectifier is specially designed for medical implant systems. It provides 1X/3X dual output voltage (1.99V and 6.29V) allowing the implantable neuromodulation system to operate with high power conversion efficiency (PCE) while stimulating simultaneously. A start-up control circuit is also added to achieve robust start-up mechanism. On-chip delay compensation control is implemented to increase the conduction time, avoid reverse current, and enhance the efficiency. In addition, the rectifier can sustain a higher input inductive voltage without the overstress problem by adding cascode power transistors. The measured dual output voltages of the 1X/3X rectifier are 1.99V and 6.29V while the input inductive voltage is 2.75V. The proposed rectifier achieves 84.2% in PCE with total 57mW output power under 13.56 MHz operation frequency. Based on its capability to provide large output voltage for stimulation with high PCE, the proposed 1X/3X active rectifier is suitable for implantable neuro-modulation systems.

Summary form only given. Biomedical application will be one of the most important applications in VLSI design field near future, and this special session informs you the hottest biomedical applications related to artificial vision systems and brain machine interface. We invite three speakers Prof. Ohta from Japan, Prof. Suaning form Australia, Prof. Wu from Taiwan, and a keynote speaker Dr. Torres-Martinez from France as leading authorities of this field to have panel discussion. Attendee will enjoy the information of the state of the art of this area all over the world and get information for difficulties and challenging to develop biomedical application systems and biomedical application itself.

This paper presents the closed-loop neural disorder control concept and some design considerations. Two architectures of closed-loop neuromodulation for Parkinson's disease and epileptic seizure are proposed. One is a closed-loop deep brain stimulator, which meets the IEC 60601-1 standard. The other one is an implantable SoC for epileptic seizure control, which is verified by animal experiment.

Multi-level morphological active contour algorithm (MMAC), was proposed in [3-4], to incorporate mathematical morphology for tree detection and crown delineation with the average prediction error around 4% in mountainous areas. However, two major drawbacks come with the design of MMAC algorithm, which are huge computational complexity and certain level of false alarm or omission rate. The paper provides a solution for two major problems by proposing a gradient vector flow (GVF) snake based MMAC algorithm. The GVF snake model took advantage of the gradient vector force of the LiDAR image and expand the boundary of each blob to approximate the real crown of each forest candidate. According to the experimental studies, the proposed algorithm could help improve the computational complexity and detection rate of the original MMAC algorithm effectively.

In this paper, a 16-channel analog front-end (AFE) ECoG-signal acquisition circuit for closed-loop seizure control system is presented. It is composed of 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with band-pass filters, 16 programmable transconductance-gain amplifiers, a multiplexer, a transimpedance amplifier, and a 10-bit SAR ADC. The low input-referred noise is achieved by using chopper modulation technique in AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop (ORL) is proposed to reduce output offset generated by input chopper mismatches. The digital ripple reduction loop (RRL) is also used to reduce chopper ripple. Moreover, to prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with high-voltage-tolerant switches is proposed to make the AFE amplifiers sharing the same electrode with high voltage stimulators. The fabricated AFE acquisition circuit has 49.1/59.1/67.9 dB programmable gain and 2.09uVrms input referred noise in a bandwidth 0.5-100 Hz. The measured power consumption of AFE is 3.26 uW per channel and the noise efficiency factor (NEF) is 3.78.

In this paper, an 8-channel area-efficient low-power current-mode analog front-end amplifier (AFEA) is designed for EEG signal recording. The AFEA is composed of eight capacitive coupled transconductors (CCGMs), current-mode band-pass filters (CMBPFs), and programmable current-gain amplifiers (PCGAs) with a multiplexer (MUX), a transimpedance amplifier (TIA), and an offset current cancellation loop (OCCL). The AFEA employs CCGM with only 2pF input capacitance to eliminate the electrode dc offset (EDO). The current-mode topology is adopted in the design of CCGMs, CMBPF s, and PCGAs to reduce the power consumption. The shared OCCL is designed to eliminate the output offset of CCGM, CMBPF and PCGA. The AFEA is designed and fabricated in 180-nm CMOS technology and the core area occupies only 1mm2. The measured maximum gain is 82 dB. The measured input-referred noise is 3.34μVrms within the bandwidth of 0.5-100 Hz. The measured maximum power consumption is 7.85 μW per channel under power supply of 1.2 V. The fabricated AFEA is applied to record the human EEG signal successfully.

In this paper, an 8-channel low-power analog front-end amplifier (AFEA) with time-constant-enhanced topology is proposed for neural signal acquisition. The AFEA is composed of eight time-constant-enhanced amplifiers (TCEAs) and high-pass filters (HPFs), a multiplexed transconductor (MGM) and a transimpedance amplifier (TIA). The AFEA is designed and simulated in 65nm CMOS technology. The bandwidth of the AFEA is 7 kHz, and the maximum gain is 61.2 dB with power consumption of 1.77 μW per channel. The TCEA is designed to reduce the high-pass cut-off frequency to 0.16 Hz and achieve a high gain of 50.7 dB with only 4 pF input capacitance. The power consumption of TCEA is 1.08 μW under 1-V power supply. The noise efficiency factor (NEF) of the TCEA is 2.13 with 4.46 μVrmsinput-referred noise.

An architecture of SAR ADC called the delta-modulated SAR ADC (DMSAR ADC) is proposed and designed for medical device applications. In the proposed DMSAR ADC, only the voltage difference between two successive samples is resolved to reduce the conversion steps and decrease the power consumption per channel up to 66%. The experimental chip is implemented in 0.18μm CMOS technology. At the digital supply voltage of 1.35V and Vref=1.00V, the measured power consumption per channel is 1.38μW (2.71μW) and the measured SNDR is 56.68dB (53.89 dB) for Fin=10Hz (7kHz). The ENOB is 9.12b and FoM is 39.54fJ/step.

In this paper, a new current-mode front-end amplifier for biopotential signal recording system is proposed. A current-mode preamplifier incorporates with an active feedback loop to bypass any dc current generated by tissues is designed as the first stage. A programmable gain stage and a current-mode filter are designed to adjust both gain and the low-pass cutoff frequency, respectively. The current-mode front-end amplifier is designed and fabricated in 0.18-μm CMOS technology. The measured maximum current gain is 55.9 dB. The high-pass cutoff frequency can achieve as low as 0.3Hz and the low-pass cutoff frequency can be adjusted from 1 KHz to 10 KHz. The measured input-referred noise is 153fA/√Hz, and the power consumption is 13 μW at 1-V power supply.

Two 23 GHz low-noise amplifier (LNA) have been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNAs, the structure of cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging (WLP) technology. The fabricated one-stage LNA has a good linearity where the input 1 dB compression point (IP-1dB) is -9.5 dBm and the input referred third-order intercept point (PIIP3) is +2.25 dBm. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated one-stage LNA has demonstrated a 4 dB noise figure (NF) and a 7.1 dB gain at the peak gain frequency of 23 GHz. Moreover, the fabricated two-stage LNA has the IP-1dBof -16 dBm and the PIIP3of -4.2 dBm. It drains 9.3 mA from 1-V power supply. This two-stage LNA has demonstrated a 4.4 dB NF and a 11.6 dB gain at the peak gain frequency of 23.4 GHz. The fabricated one-stage LNA has the highest figure-of-merit (FOM). The experimental results have proved the suitability of 45 nm gate length planar bulk-CMOS devices for RF ICs above 20 GHz.

A new linear current mode image sensor is proposed in this paper. The proposed circuit features high linearity, low power consumption, programmable multiple gain stages, wide input swing and correlated double sampling (CDS) technology. The signal swing of the linear current mode sensor is enhanced by the proposed multiple gain readout structure. A simple and accurate front-end programmable gain structure is proposed to improve the signal-to-noise ratio (SNR) with low power consumption. The function and performance has been verified by HSPICE simulation of 0.18 mum 3T sensor process.

The CMOS integrated 3-GHz to 11-GHz transmitter for full-band UWB applications is proposed and designed in 0.13-μm CMOS technology. The designed UWB transmitter is integrated with a 2:1 frequency divider, a quadrature up-conversion mixer, a balanced RF amplifier, and a 3-stage cascaded poly-phase filter. The technique of inductance peaking has been adopted to achieve 14-band operation for UWB applications. The transmitter has an average conversion gain of 12.8 dB with the gain ripple of around ±1.4 dB among the whole frequency band. The average input 1-dB compression point (IP. 1dB) of the 14 bands is −12.2 dBm and the average output 1-dB compression point (OP-1dB) of the 14 bands is −0.4 dBm. The transmitter dissipates the power of 53.1 mW from the supply voltage of 1.2 V and occupies the chip area of 1930×1635 μm2. This chip is designed in 0.13-μm 1P8M CMOS technology and under fabrication.

A design of CMOS expansion/contraction motion sensor based on the artificial retinal sensor array and digital correlation circuitry for real-time detecting object motion and velocity in the longitudinal +Z/-Z-directions (Z-motion) is proposed. To cope with the non-uniform nature in optic field of Z-motion, we compute the correlation between one set of output of retinal sensors and the delayed output of the other set of far-end sensors at progressive increasing distances across the chip for motion and velocity detection. Sweeping the correlation delay value in one signal path of the correlator, the chip can indicate the strongest correlation when the correlation delay is tuned to match the actual velocity. Behavior-level MATLAB simulations have been performed to successfully validate the functionality of the proposed motion detection method using expanding or contracting motion images that are incurred from an out-bound or in-bound moving object at a constant Z-velocity. The proposed motion sensor consists of 1448 sensor pixels placed on thirty-two evenly spaced divergent axes with 25 correlator outputs on each axis. Z-motion and velocity detection is performed based on the maximum likelihood (ML) detection using the 25 correlators output of all 32 axes. The chip is designed in 0.35-μm CMOS technology and the core occupies approximately 5600×5600 μm2with a fill factor of 11%.

A new 24-GHz CMOS current-mode power amplifier in 0.13-μm CMOS technology is proposed. By using the two-stage cascade current-mirror structure, the power amplifier has a maximum output power of 17.8 dBm, the OP1dBof 13.8 dBm and the power gain of 23 dB under the supply voltage of 1.2V and the total power dissipation of 239 mW. As compared to other PAs at 17~24 GHz, the proposed current-mode PA has the highest power added efficiency (PAE) of 34.6% and the largest output power.

In this paper, a novel large neighborhood cellular nonlinear network (LN-CNN) structure is proposed and analyzed. The proposed LN-CNN structure can realize both A and B templates with more than two neighborhood layers without complex direct connections between neural cell and neighboring cells. In both A and B templates, the first layer defined by 4 neighboring cells located at the 4 corners of a diamond shape whereas the second layer is defined by 8 cells. In realizing the 12 template coefficients of the template, only 8 connections are required as compared to 12 connections in the conventional CNN structure. Thus the required chip area for synaptic connection can be reduced, Using the proposed LN-CNN structure, the LN-CNN functions, such as noise removing, Muller-Layer arrowhead illusion, and connected component detection, have been successfully realized and verified in Matlab simulations. The constraints on the realized templates and template coefficients in the third or higher layers are analyzed and discussed. Based upon the above successful simulation results, the application of the proposed LN-CNN structure to the design of LN-CNN universal machine (LN-CNNUM) is quite feasible. The related research will be conducted in the future.

In this work, a bionic sensory chip based on the CNN model derived from the mammalian retina is proposed. A CMOS compatible sensory chip is designed based on the CNN model to mimic functions of photoreceptor and horizontal cell of the mammalian retina. The sensory chip contains a focal plane array of 32/spl times/32 similar pixels that perform functions of photoreceptor and horizontal cell. Spatial and temporal characteristics of a one-dimensional array are verified via HSPICE simulations in this paper, while a two-dimensional array of 32/spl times/32 cells is to be fabricated to investigate real-time images obtained by this bionic sensory chip.

A compact 2 V CMOS low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator (VCO) and RF amplifier for 1.9 GHz RF transmitter applications is described. The circuit is implemented by using 0.35 /spl mu/m DPTM CMOS technology and dissipates only 19 mW under 2 V power supply voltage. The low power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Due to small signal path mismatch, the unwanted lower sideband is below -50 dB when the 0 dB normalized desired upper sideband is set at 1.97 GHz. Moreover, the LO feedthrough, second-order intermodulation, and third-order intermodulation are less than -50 dB. The tuning range of the quadrature VCO is 270 MHz from 1.95 GHz to 2.22 GHz.

An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1 V. The device dimension (W/L) of the ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (/spl mu/m//spl mu/m) in a 0.35 /spl mu/m silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only /spl sim/1.0 pF (including the bond pad capacitance) for high-frequency applications.

A new CMOS fully differential bandpass amplifier (BPA) based on the structure of a transresistance (Rm) amplifier and capacitor is proposed and analyzed. In this design, the Rm amplifier is realized by a simple inverter with tunable shunt-shunt feedback MOS resistor and tunable negative resistance realized by the cross-coupled MOS transistors in parallel with a current source. The capacitor is in series with the input of the Rm amplifier, which realizes the filter function and blocks the DC voltage. Under a 2 V supply voltage, the post-tuning capability of the gain can be as high as 90 dB whereas the tunable frequency range is between 41 MHz and 178 MHz. The power consumption is 11 mW and the dynamic range (DR) is 50 dB. The differential-mode gain is 20 dB and the common-mode gain is -25 dB so that the CMRR is 45 dB. Simple structure, good frequency response and low power dissipation make the proposed bandpass amplifier guite feasible in the applications of an IF stage for RF receivers.

By incorporating the basic constant current (CC) configuration with the buffered direct injection (BDI) structure, a new readout circuit called the constant current buffered direct injection (CCBDI) is proposed for the uncooled bolometer detector FPAs. Due to the use of BDI structure, the offset is decreased and the linearity range is increased. Thus linearity, dynamic range, and uniformity are improved. An experimental chip of 64/spl times/64 CCBDI FPA readout circuit has be designed and fabricated by using 0.5 /spl mu/m double-poly double-metal n-well CMOS technology with the cell size of 50/spl times/50 /spl mu/m/sup 2/. The measured linearity is 94.36% whereas the measured uniformity is 81.3%. Both measurement and simulation results have verified the advantageous features of the proposed CCBDI readout circuit. It is believed that the new CCBDI structure has a great potential in the applications of large uncooled bolometer FPAs.

In this paper, two CMOS implementations of the cellular neural network (CNN) are presented based on the neuron-bipolar junction transistor (/spl nu/BJT) which consists of the parasitic PNP bipolar junction transistor and the spreading base resistor array in the CMOS process. In the first design, the /spl nu/BJT is used to implement the neuron and weights of the cell. In the second design, it is used to implement the current summation and weights of the cell, and a diode structure is proposed to realize the neuron. For programmable capability the resistor in the /spl nu/BJT can be replaced by a tunable MOS resistor. The two kinds of circuits have been designed and fabricated in 0.6 /spl mu/m single-poly-triple-metal n-well CMOS process.

An improved bipolar junction transistor (BJT) based silicon retina with simple and compact structure is proposed and analyzed. In the proposed structure, the BJT smoothing network, which models the layer of horizontal cells in the vertebrate retina, is implemented by placing enhancement n-channel MOSFETs among the bases of parasitic BJTs existing in a CMOS process to form an unique and compact structure. Thus, the smoothing characteristics can be tuned in a wide range. Moreover, an extra emitter is incorporated with each BJT at the pixel to act as the row switch. This reduces the cell area of the silicon retina and increases the resolution. Using the proposed new structure, an experimental 64/spl times/64 BJT-based silicon retina chip has been fabricated by using 0.5-/spl mu/m CMOS technology. The measurement results on the tunability of the smooth area in the smoothing network as well as the dynamic characteristics of the proposed silicon retina in detecting moving objects have been presented. It is believed that the improved structure is very suitable for the very large scale integration implementation of the retina and its application systems for CMOS smart sensors.

A discussion of CMOS readout technologies for infrared (IR) imaging systems is presented. First, the description of various types of IR detector materials and structures is given. The advances of detector fabrication technology and microelectronics process technology have led to the development of large format array of IR imaging detectors. For such large IR FPAs which is the critical component of the advanced infrared imaging system, general requirement and specifications are described. To support a good interface between the FPA and downstream signal processing stage, both conventional and CMOS readout techniques are presented and discussed. Finally, future development directions including the smart focal plane concept are also introduced.

A new design methodology is proposed to realize a real cochlea using the multiplexing switched-capacitor circuits. The proposed technique is based upon the transmission-line model proposed by Zwislocki (1950). At the cost of the increase in the number of clock phases, the decay rate in the transition region of the filter section can be increased by adding only a few components. Therefore, the components and chip area of the designed silicon cochlea can be small. An experimental chip containing four filter sections has been designed and fabricated. The measured frequency responses from the 32-section cochlea formed by cascading nine fabricated chips are consistent with both theoretical calculation results and observed behavior of a real cochlea. Moreover, the designed silicon cochlea has the dynamic range of 67 dB in each section and a low sensitivity to process variations. Thus it is suitable for VLSI implementation with the associated neural network.

Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory. It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode analog dividers are developed to implement the special memory called the ratio-type memory. Furthermore, a CMOS current-mode analog multiplier is used to implement the correlation. The implemented CMOS outstar can on-chip store the relative ratio values of the trained weights for a long time. It can also be modularized to construct general neural nets. HSPICE (a circuit simulator of Meta Software, Inc.) simulation results of the CMOS outstar circuits as associative memory and pattern learner have successfully verified their functions. The measured results of the fabricated CMOS outstar circuits have also successfully confirmed the ratio memory and on-chip learning capability of the circuits. Furthermore, it has been shown that the storage time of the ratio memory can be as long as five minutes without refreshment. Also the outstar can enhance the contrast of the stored pattern within a long period. This makes the outstar circuits quite feasible in many applications.

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.

A new cyclic Analog-to-Digital conversion algorithm with embedded digital error correction is proposed to reduce the linearity errors caused by the comparator inaccuracy and the offset of the S/H operations. New low-voltage fully-balanced current-mode circuits performing the sample/hold, signal-amplification, and current comparison functions are developed to realize a low-voltage current-mode cyclic Analog-to-Digital converter (ADC). With 1.5 V supply voltage and 0.8 /spl mu/m CMOS device parameters, the HSPICE simulation results show that the designed ADC can achieve 12-bit resolution at 10 k/s conversion rate with the power dissipation of the analog circuits less than 2 mW.

There is one LVTSCR (Low Voltage Trigger SCR) device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to V/sub SS/ and V/sub DD/ powerlines. The DC switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it has an excellent ESD protection capability in a smaller layout area.

A low-voltage very high-frequency CMOS lowpass biquad filter using simple transconductance (Gm) amplifier and transresistance (Rm) amplifiers is proposed and analyzed. Both single-ended and fully-differential topologies have been developed in this paper. Simulation results show that for the single-ended lowpass biquad filter, the center frequency fo can be tuned from 123 MHz to 181.9 MHz whereas the power dissipation varies from 2.92 mW to 3.36 mW. For 1% THD, the equivalent maximum output signal of the single-ended filter with center frequency 181.9 MHz is about 67 mV with a 2.5 V power supply. For the fully-differential lowpass biquad filter, the center frequency fo can be tuned from 124 MHz to 218.7 MHz whereas the power dissipation varies from 7.94 mW to 9.44 mW. For l% THD, the equivalent maximum output swing of the fully-differential filter with center frequency 218.7 MHz is about 414 mV under fully-balanced inputs with a 2.5 V power supply.

A new pass-transistor logic called the current-sensing complementary pass-transistor logic tree (CSCPTL) is proposed and investigated. The new logic circuit can be used in low-voltage low-power systems for high-speed applications. To examine the low-voltage applications, a 1.2 V supply voltage is selected for one battery back-up systems. The current-sensing scheme yields a good sensing speed with small voltage swing. The dc power dissipation of the current mode circuit makes it difficult to apply in low power applications. The new circuit can resolve the dc power problem in the current-sensing scheme. The new circuit has superior speed performance with a power-delay product comparable to LCPL which is acknowledged to have the most potential in low-voltage low-power digital circuits design. The CSCPTL can be operated at 1.2 V without changing the conventional 5 V CMOS process.

A 1.5 V SC filter employing a balanced differential structure and a internal clock booster is proposed. The design technique is demonstrated by a fourth-order bandpass biquad filter fabricated with a standard 0.8 /spl mu/m CMOS technology. This prototype fourth-order filter which has a center frequency of 8 kHz and a clock frequency of 400 kHz dissipates about 330 /spl mu/W with a 1.5 V power supply. Including the clock generator and boosters, it occupies 600/spl times/1500 /spl mu/m/sup 2/. The measurement result shows this filter has the IMD of 0.1 percent for 1.2 V/sub IP/ differential signal.

This paper describes a new SC method to reduce the capacitor mismatching error and finite-gain error in an ADC. Through the use of switched-capacitor techniques, the proposed new ADC is insensitive to the capacitor-ratio accuracy as well as the finite gain and the offset voltage of the operational amplifiers. The switching error becomes the only major error source. Moreover, the cycle time for n-bit conversion is reduced to 4n-clock time. Both SWITCAP and HSpice simulations have been performed to verify the performance of the new ADC. It is shown that a 15-bit resolution at the sampling frequency of 20 KHz can be achieved when the capacitor ratios have a variation of 1% and the finite gain of the op amps is only 65 dB.>

A set of new CMOS differential logic circuits are proposed for the true-single-phase clocking scheme in the pipelined systems. All the new logic circuits are insensitive to the clock slopes and free from race problem. Using the new logic circuits, the clock loading can be greatly reduced. They can be applied to high-packing-density and high-speed CMOS pipelined systems. An experimental chip has been fabricated and measured, which partly verifies the performance of the new logic circuits.>

A CMOS generic analog processor, using the current-mode design technique, is described. The processor integrates various functions frequently used in analog computing and signal processing. Its operation can be programmed by digital control signals. Furthermore, it provides serial output as well as parallel outputs, and can be expanded to a larger system by connecting the serial ports of the chip sets together. An experimental chip fabricated using 0.8 /spl mu/m CMOS process can perform generic functions up to 5M operations per second. The chip has an area less than 3 mm/sup 2/.>

A new CMOS inverter-based wideband transresistance (R/sub m/) amplifier is proposed and analyzed. Using the R/sub m/ amplifier, tunable VHF/UHF R/sub m/-C bandpass biquadratic filters can be designed. In these filters, the center frequency f/sub 0/ can be post-tuned by adjusting the control voltages of the R/sub m/ amplifier. Experimental results have shown that the single-ended-output R/sub m/-C bandpass biquad has the center frequency f/sub 0/=368 MHz and the quality factor Q=1.95 whereas the fully-differential-output configuration has Q=360 and f/sub 0/=222.7 MHz.>

This paper describes a new feedback-controlled enhanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and bipolar transistor saturation during operation period is avoided. Based upon the proposed. Structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XOR/XNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3-input XOR/XNOR gates at 2.4 V supply voltage.>

A linear wideband class AB finite-gain current amplifier is proposed and analyzed. Considering the intrinsic capacitance of the MOS transistors as filter elements, the current amplifier can be viewed as a VHF lowpass biquad filter. The center frequency fo is tunable from 79.4 MHz to 144.5 MHz and the quality factor Q is tunable from 1.03 to 1.19. A linear wideband class AB finite-gain voltage amplifier is also proposed and analyzed. Similarly, the unity-gain voltage amplifier can also be regarded as a VHF voltage biquad lowpass filter with the center frequency tunable from 81 MHz to 134.89 MHz and the quality factor tunable from 1.12 to 1.59. A new and special Q-enhancement circuit is also proposed to increase the center frequency fo and enhance the quality factor Q of the VHF filters. It is shown that the center frequency fo is tunable from 173.78 MHz to 205.6 MHz and the quality factor Q tunable from 1.69 to 7.21.>

Efficient physical timing models for complex CMOS AND-OR-inverter (AOI) and OR-AND-inverter (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS AOI/OAI gates with wide ranges of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and noncharacteristic waveform input excitations. The error can be further reduced to 16% with the commonly used device dimensions. The developed timing models are successfully applied to the autosizing of CMOS AOI/OAI gates. The results show a good accuracy and a reasonable CPU time consumption.>

A new general timing model for CMOS combinational logic gates is proposed. In this model, the linearized large-signal equivalent circuit of a gate is first constructed. Then applying the dominant-pole-dominant-zero (DPDZ) method, the dominant pole of the equivalent circuit is calculated. Using this pole, the signal timing can be explicitly expressed. Comparisons between calculation results and simulation results are made and error analyses are performed. The worst-case error in characteristic-waveform timing can be confined to be within 35 percent for CMOS inverters, multi-input NOR gates or multi-input NAND gates with different device dimensions, capacitive loads, and device parameters. Better accuracy can be obtained for logic gates with commonly-used channel dimension or large capacitive load. For internal waveforms not deviating much from the characteristic waveforms, the worst-case error in signal timing is not substantially increased. Applying the proposed timing model in an experimental timing simulator, the signal timing can be analyzed accurately and efficiently with reduced CPU time and memory.