EDBT 2026 Demo / reviewers in the wild / expert
Xiaohua Zheng
dblp:07/10384
· DBLP profile ↗
2ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 75% Performance modeling and evaluation · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.7 | 1 | 2023 | Accelerating Loop-Oriented RTL Simulation With Code Instrumentation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation
high-level synthesis |
0.7 | 1 | 2023 | Accelerating Loop-Oriented RTL Simulation With Code Instrumentation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Electronic design automation › hardware verification and test › hardware verification
RTL simulation |
0.7 | 1 | 2023 | Accelerating Loop-Oriented RTL Simulation With Code Instrumentation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Performance modeling and evaluation › simulation › architectural simulation
simulation acceleration |
0.7 | 1 | 2023 | Accelerating Loop-Oriented RTL Simulation With Code Instrumentation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Methods — techniques the papers use, named apart from their topics
performance prediction model · 0.7code instrumentation · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Accelerating Loop-Oriented RTL Simulation With Code InstrumentationabstractThe hardware description of circuits usually contains many loops. Register transfer level (RTL) simulation is a critical step to verify the correctness of circuits and is time consuming. Thus, it is necessary to speed up its process. However, the speedup of existing RTL simulation acceleration techniques is usually small. Although the speedup of hardware acceleration is large, the hardware cost is high. Some methods utilize performance models without performing RTL simulation to obtain rough simulation performance and have a large speedup. However, they do not support functional verification. In order to address the problems, we propose a loop-oriented RTL simulation acceleration approach based on code instrumentation for designs synthesized by high-level synthesis. Our approach reduces the RTL simulation time by skipping a large number of repeated loop iterations, and maintains high accuracy for the prediction of the number of cycles by reserving some loop iterations. We establish a performance prediction model and an interval value formula for skipping loop iterations. We conduct experiments on the MachSuite benchmark. The results show that for the RTL simulation of single data processing and batch data processing, the average speedup of our approach can reach$7.49\times $and$43.3\times $, respectively, and the average prediction errors of the number of cycles are 1.71% and 1.06%, respectively. It also reveals that the interval value obtained by our approach for skipping loop iterations can quickly and effectively balance between the accuracy of prediction of the number of cycles and speedup. Compared to the state-of-the-art approach ESSENT, the speedup of our approach is better and the accuracy of prediction of the number of cycles remains at the same level as that of performance models. Fubing Mao, Yapu Guo, Xiaofei Liao, Hai Jin 0001, Wei Zhang 0012, Haikun Liu, Long Zheng 0003, Zihan Jiang 0001, Xiaohua Zheng |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 10 |
| 2020 | Visually Consistent Color Correction for Stereoscopic Images and VideosabstractIn stereoscopic 3D (S3D) color correction, visual inconsistency is a common problem that leads to perceptual quality degradations. In this paper, we propose an S3D image/video color correction strategy that resolves global, local, and temporal color discrepancies simultaneously. We achieve the image-based S3D color correction by three steps: a coarse-grain color correction for global color matching, a fine-grain color correction to further improve both global and local color consistencies, and a guided filtering process to guarantee the structural consistency before and after color correction. In addition, we extend the above strategy to S3D and multiview video color correction. To achieve temporal consistency between successive video frames, we develop an improved histogram matching within a sliding window on time axis. In our method, the mapping functions for each color channel change gradually following the video stream to avoid abrupt temporal changes in colors. The experimental results demonstrate that the proposed strategy outperforms the state-of-the-art color correction algorithms for images and videos. Yuzhen Niu, Xiaohua Zheng, Tiesong Zhao |
IEEE Trans. Circuits Syst. Video Technol. | 2 |