We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed circuit topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of trapezoidal-wave clock signals. We have tested the driver with a capacitive load between 38.3 and 97.8 pF with clock frequency ranging between 0.8 and 15 MHz. The overall power dissipation for our second-order harmonic rail driver is 19% of fC/sub L/V/sup 2/ at 15 MHz and 97.8 pF load.

This paper describes compact mathematical models for estimating the frequency performance and power dissipation of a micro-processor as a function of the supply voltage. The objective is to estimate the frequency and/or power performance across a wide range of supply voltages and operating frequencies using only a small number of configurable parameters and equations. These compact equations are amenable to hand calculations and spreadsheet manipulation. The configurable parameters are derived from actual measurements of microprocessor chips and are calculated using the least-squares curve-fitting method.

Article Share on Theory and practical implementation of harmonic resonant rail driver Authors: Joong-Seok Moon University of Southern California, Los Angeles, CA University of Southern California, Los Angeles, CAView Profile , William Athas Apple Computer Inc., Cupertino, CA Apple Computer Inc., Cupertino, CAView Profile , Peter Beerel University of Southern California, Los Angeles, CA University of Southern California, Los Angeles, CAView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 153–158https://doi.org/10.1145/383082.383122Published:06 August 2001Publication History 2citation169DownloadsMetricsTotal Citations2Total Downloads169Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that can efficiently inject and extract energy, and an efficient power delivery system to connect the power source to the circuit nodes. The additional circuitry and timing required to support this process can readily exceed the power-savings benefit. Clock-powered logic is a circuit-level, energy-recovery approach that has been implemented in two generations of small-scale microprocessor experiments. The results have shown that it is possible and practical to extract useful amounts of power savings by leveraging the additional circuitry for other compatible purposes. The capabilities and limitations of clock-powered logic as a competitive low-power approach are presented and discussed in this paper.

Retractile clock-powered logic is presented as a low-overhead energy-recovery logic style.It uses energy-efficient clock-steering circuits, pass-transistor logic, and a fourphase clocking scheme to recover energy from all circuit nodes but the latches.A 16-bit retractile clock-powered adder is described and evaluated through HSPICE simulations.The simulation results indicate that this approach can offer superior energy vs. delay performance but the benefit depends strongly on the switching activity of the clock-powered nodes.

Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth requirements.The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect.DIVA increases memory bandwidth through two mechanisms: (1) performing selected computation in memory, reducing the quantity of data transferred across the processor-memory interface; and (2) providing communication mechanisms called parcels for moving both data and computation throughout memory, further bypassing the processor-memory bus.DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations.In this paper, we focus on several aspects of DIVA designed to effectively support such computations at very high performance levels: (1) the memory model and parcel definitions; (2) the PIM-to-PIM interconnect; and, (3) requirements for the processor-to-memory interface.We demonstrate the potential of PIMbased architectures in accelerating the performance of three irregular computations, sparse conjugate gradient, a natural-join database operation and an object-oriented database query.

We describe the design of AC-l, a low-power 16-bit microprocessor which utilizes clock-powered logic to reduce dissipation in its power-intensive sections.We present power measurements for a 0.5~pm n-well CMOS implementation.A resonant clock driver recovers and reuses energy that would otherwise be dissipated as heat, yielding measured overall power reduction factors of four to five.-.--.----* ~ .i~

We compare the frequency-versus-power dissipation performance of two energy-recovery CMOS implementations to that of a conventional, supply-voltage-scaled design. The application is a small but complete DSP function. All three designs are based on the same high-level organization and conform to the same I/O specification. SPICE simulations indicate that an energy-recovery design which requires only a small degree of modification to the conventional design offers more than a two-fold reduction in power across a wide range of operating frequencies.

We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 × 256 memory configuration indicate that, for successive write operations, energy saving for the different SRAM functions vary from 59% to 76% at 200 MHz operating frequency compared to the conventional design.

In this paper, an 8-bit energy-recovery adder design is evaluated through SPICE simulation for energy dissipation and delay time, and is compared against a supply-voltage-scaled adder. The experimental results indicate that the energy-recovery adder outperforms the supply-scaled version for a wide range of frequencies.

Describes a custom CMOS line driver chip and a resonant power supply that can switch eight 100 pF loads at 1 MHz six times more efficiently than a conventional (CV/sup 2/) CMOS solution. The authors describe the adiabatic charging principle used, which allows a digital circuit designer to directly trade off switching time for increased energy efficiency. Emphasis is placed on evaluating the dissipation overhead for the whole system including the power supply. Measurements confirm the predicted dissipation decrease.>

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead.>

In any stored-program computer system, information is constantly transferred between the memory and the instruction processor. Machine instructions are a major portion of this traffic. Since transfer bandwidth is a limited resource, inefficiency in the encoding of instruction information (low code density) can have definite hardware and performance costs.