The Tera ATM LAN project at Carnegie Mellon University addresses the interconnection of hundreds of workstations in the Electrical and Computer Engineering Department via an ATM-based network. The Tera network architecture consists of switched Ethernet clusters that are interconnected using an ATM network. This paper presents the Tera network architecture, including an Ethernet/ATM network interface, the Tera ATM switch, and its performance analysis. The Tera switch architecture for asynchronous transfer mode (ATM) local area networks (LAN's) incorporates a scalable nonblocking switching element with hybrid queueing discipline. The hybrid queueing strategy includes a global first-in first-out (FIFO) queue that is shared by all switch inputs and dedicated output queues with small speedup. Due to hybrid queueing, switch performance is comparable to output queueing switches. The shared input queue design is scalable since it is based on a Banyan network and N FIFO memories. The Tera switch incorporates an optimal throughput multicast stage that is also based on a Banyan network. Switch performance is evaluated using queueing analysis and simulation under various traffic patterns.>

A new nonblocking copy network is presented, for use in an ATM switch supporting BISDN, with a shared-memory input buffer. Blocked cells from any switch input are stored in a single shared input buffer. The copy network consists of three Omega networks and shared-memory queues. The design is scalable for large numbers of inputs due to a low hardware complexity, O(N log/sub 2/ N), and distributed operation and control. It is shown by simulation results that a switch incorporating the shared-memory copy network has increased throughput and lower buffer requirements to maintain low packet loss probability when compared to a switch with a discrete buffer copy network.>

As dependence on wide-area and other point-to-point networks increases, the need for diagnosis of the distributed resources becomes critical. Continuous online distributed diagnosis at the system-level provides a desirable solution. The Adapt algorithm, which performs online adaptive distributed diagnosis in arbitrary networks in the presence of node failures, is examined. Simulation results depicting operation for various network topologies are given, including test and message counts and diagnosis latency. The results indicate that Adapt performs significantly better than derived worst-case bounds. The best- and worst-case performance bounds are analyzed.>

The practical application and implementation of online distributed system-level diagnosis theory is documented. Proven distributed diagnosis algorithms are shown to be impractical in real systems due to high resource requirements. A distributed system-level diagnosis algorithm called Adaptive DSD is shown to minimize network resources and has resulted in a practical implementation. Adaptive DSD assumes a distributed network, in which network nodes can test other nodes and determine them to be faulty or fault-free. Tests are issued from each node adaptively and depend on the fault situation of the network. Test result reports are generated from test results and forwarded between nodes in the network. Adaptive DSD is proven correct in that each fault-free node reaches an accurate independent diagnosis of the fault conditions of the remaining nodes. No restriction is placed on the number of faulty nodes; any fault situation with any number of faulty nodes is diagnosed correctly. An implementation of the Adaptive DSD algorithm is described.>

The design and implementation of a high-performance special-purpose processor, called the White Dwarf, or accelerating finite-element analysis algorithms is presented. The White Dwarf CPU contains two Am2935 32-bit floating-point processors and one Am29332 32-bit arithmetic logic unit (ALU), and uses a wide-instruction-word architecture in which the application algorithm is directly implemented in microcode. The entire system is VME-bus compatible and interfaces with a Sun 3/160 host. The system's potential peak performance is 20 MFLOPS (million floating-point operations per second) a sustained computation rate in excess of 15 MFLOPS is expected. A potential speedup of between one and two orders of magnitude is possible. With a fully populated memory subsystem, the White Dwarf can accommodate finite-element problems involving up to half a million nodes. The system is designed using an approach called application-specific processor design (ASPD). A retargetable compiler has been developed which is capable of generating highly parallel and efficient code for the White Dwarf and other processors with similar architecture. System debug/integration is in progress; a highly useful system is expected.>

Recent research on parallel systems has shown that the most difficult problem for system designers and users is interprocessor connection and communication. A methodology for the automated design and implementation of interprocessor communication for certain multiple-processor systems has been developed and is presented in this paper. For many application- specific and mission-oriented systems, the interprocessor communication is deterministic and can be specified at system inception. This specification can then be automatically mapped or complied onto a physical multiple-processor system using a network traffic scheduler. An algorithm for such a scheduler, which is capable of obtaining optimal network traffic patterns, has been developed. It is shown that the order of complexity of network scheduler components is polynomial, rather than expopential as in classical solutions.