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Nobutaka Imamura

dblp:07/1948 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1Graphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 44% Parallel and multicore computing · 44% Interconnection networks and networks-on-chip · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › multiprocessor system
distributed memory parallel computers
0.011994
AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994
Processor architecture and microarchitecture
instruction set architecture
0.011994
AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994
Interconnection networks and networks-on-chip › interprocessor communication
message-passing network
0.011994
AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler · ASPLOS 1994

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
2020 NAS-EOD: an end-to-end Neural Architecture Search method for Efficient Object Detection
abstract
Model efficiency for object detection has become more and more important recently, especially when intelligent mobile devices get more and more popular. Current lightweight object detection model is either migrated from lightweight classification models, or pruned directly from complex object detection models. These pipelines can not match the performance requirements of edge devices. In this work, we propose a neural architecture search (NAS) method to build a detection model automatically that can perform well on edge devices. Specifically, the proposed method supports the search of not only multiscale feature network, but also backbone network. This enables us to search out a global optimal model. To this end, we've made a special design that the backbone and feature network can share the same search space. This method greatly reduces the search time while ensuring the search accuracy. It can find a good architecture in 14GPU days. Additionally, we add latency information into the main objective during performance estimation. Therefore, we can control between the speed and accuracy to better adapt to the edge environment. Experiments on the PASCAL VOC benchmark indicate that the searched architecture (named NAS-EOD) can get good accuracy even if training from scratch. When using a pre-training scheme, our model is superior to state-of-the-art small object detection models.
Huigang Zhang, Liuan Wang, Jun Sun 0004, Li Sun 0007, Hiromichi Kobashi, Nobutaka Imamura
ICPR6
2006 Grid Service Platform: Design and Implementation of Grid Middleware for Telecom Carriers
abstract
We have developed the Grid Service Platform (GSP), which is a grid middleware for telecom carriers. GSP can support not only non-interactive batch style services, but also interactive real-time services. Moreover, GSP attains autonomous resource sharing between services based on the priority of each service. We conducted a field trial of GSP on a testbed that consisted of three sites in Japan and France. Two different types of services were implemented on GSP: a video conferencing service (interactive) and a batch queuing service (non-interactive). As a result, the performance of both services were simultaneously enhanced. The session capacity of the video conferencing service was improved by up to 30%, while the total execution time of batch jobs was reduced by 12%.
Soichi Shigeta, Nobutaka Imamura, Haruyasu Ueda, Hiromichi Kobashi, Miho Murata, Taketoshi Yoshida, Atsushi Kubota, Akira Asato, Yoshimasa Kadooka
e-Science2
1994 AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler
abstract
The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+.
Kenichi Hayashi, Tsunehisa Doi, Takeshi Horie, Yoichi Koyanagi, Osamu Shiraki, Nobutaka Imamura, Toshiyuki Shimizu, Hiroaki Ishihata, Tatsuya Shindo
ASPLOS6