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Jayawant Kakade

dblp:07/2628 · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 first-authorSoftware engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.222008
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Minimization of Linear Dependencies Through the Use of Phase Shifters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › hardware verification and test
fault coverage
0.222008
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Minimization of Linear Dependencies Through the Use of Phase Shifters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation
hardware verification and test
0.222008
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Minimization of Linear Dependencies Through the Use of Phase Shifters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007
Electronic design automation › hardware verification and test
test generation
0.222008
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Minimization of Linear Dependencies Through the Use of Phase Shifters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007

Methods — techniques the papers use, named apart from their topics

phase shifter analysis · 0.1hardware cost comparison · 0.1generalized LFSR design · 0.1phase shifter design · 0.1linear algebra over GF(2) · 0.1
YearPublicationVenuePosition
2008 Deterministic Built-in TPG with Segmented FSMs
abstract
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number riof unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM) with log2riflip-flops. As all FSMs run through their states, all patterns of T are generated in time R. Experimental results show that with appropriate filling of the don't cares to reduce the number of representatives in each segment, and with the use of standard sequential synthesis tools, the scheme can offer low hardware overhead as well as low number R of test cycles.
Samara Sudireddy, Jayawant Kakade, Dimitrios Kagaris
IOLTS2
2008 Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs
abstract
Linear finite-state machines (LFSMs) such as linear feedback shift registers (LFSRs), cellular automata (CA), and ring generators (RGs) are used as test pattern generators in built-in self-test schemes that employ 2-D scan design. These mechanisms are usually accompanied by phase shifters (PSs) in order to avoid the degradation of the fault coverage caused by correlations/dependences in the produced test bit sequences. Given this context, we investigate in this paper the potential of generalized (or Galois) LFSRs (GLFSRs) as onboard test pattern generators. We compare GLFSRs with and without PSs against LFSMs with PSs (LFSM/PSs) for various types of LFSMs (LFSRs, CA, RGs, and dense RGs) on two accounts: channel separation and overall hardware cost. Experimental results show that GLFSRs achieve larger channel separation with lower hardware cost than LFSM/PS and attain higher fault coverage.
Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2007 Cellular Automata with Large Channel Separations
abstract
In built-in 2D test pattern generation, parallel scan chains are driven by successive stages of a TPG mechanism. The bit sequences received by the scan chains are shifted versions of one another by different numbers of bit positions known as phaseshifts. Small phaseshifts impact negatively the fault coverage, and in order to alleviate this problem, the use of additional hardware overhead in terms of multi-input XOR gates (phaseshifters) has been proposed in the literature to impose large phaseshifts. In this paper we show that by simply permuting locally the stages of a cellular automaton and adding absolutely no other logic, large phaseshifts can be attained. In particular we show that scan chain i can be driven by an appropriate CA stage j, such that |j - i| les B and the minimum phaseshift between successive chains (channel separation) is maximized. The user-defined bound B controls the routing overhead. We have obtained large channel separations even for B = 2.
Jayawant Kakade, Dimitrios Kagaris
ISCAS2
2007 Minimization of Linear Dependencies Through the Use of Phase Shifters
abstract
Two-dimensional scan design with a linear test pattern generator is a practical built-in self-test technique, but it suffers from linear dependencies, which reduce the fault coverage. To alleviate this problem, networks of xor gates known as phase shifters can be employed. Current techniques based on the empirical criterion of imposing large phase shift differences (channel separations) between successive scan chains cannot adequately remove the dependencies. In this paper, we present a method that addresses explicitly the minimization of linear dependencies through appropriate selection of phase shift values. The method is based on the criterion of minimizing the linear dependencies in each cone of the circuit under test, and is applicable to any type of linear test pattern generator, be it linear feedback shift register of the external- xor or internal-xor type, cellular automaton, etc. Experimental results demonstrate the effect of the approach in increasing fault coverage.
Jayawant Kakade, Dimitrios Kagaris
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2006 Phase shifts and linear dependencies
abstract
Two-dimensional scan design is a widely used BIST architecture for pseudo-random and pseudo-exhaustive testing. However, linear dependencies that arise due to the properties of the test-pattern generators in use have a negative impact on fault coverage. To alleviate this problem, networks of XOR gates known as phase shifters are often used. Existing techniques for selecting phase shifts, such as those based on large channel separations, lead to inadequate removal of linear dependencies. In this paper we present for the first time a method for the selection of appropriate channel phase shifts to explicitly minimize linear dependencies. Experimental results corroborate the effect of the approach in increasing fault coverage
Jayawant Kakade, Dimitrios Kagaris
ISCAS1